US6038181A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Efficient semiconductor burn-in circuit and method of operation
Assignee: International Business Machines Corp
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Filing: 1998-08-18
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Granted: 2000-03-14
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Expires: 2018-08-18
Abstract
Abstract The disclosed invention provides a circuit and burn-in test method for semiconductor devices that increases the speed of burn-in tests. The present invention accomplishes this by causing each of the devices under test to be tested multiple times (from 2 to 32+ times) during each power cycle. By such multiple cycling of the unit under test, during the power cycle, the total test time is shortened. It has also been found that the devices tested in accordance with the present invention are more efficiently stressed and have a reliability greater than devices passing the prior art tests. In accordance with the invention, the memory or logic devices under test are provided with a respective clock means that will operate each of the devices under test through multiple (from 2 to 32+ times) write and read operations during each power cycle. Data coherency for each read operation is provided as is the inversion of data if any fail is recorded during a read operation. Accordingly, the present invention provides a burn-in test that more efficiently stresses semiconductor devices such as memory or logic units, by a factor of up to 32. The invention utilizes the internal clock of a semiconductor device by cycling that clock x times during the period of each external clock cycle in the burn-in test and simultaneously synchronizes these internal cycles with the test cycle, thereby providing coherent data for each internal cycle.
Inventors
- 👤 George M. Braceras
- 👤 James J. Covino
- 👤 Richard E. Hee
- 👤 Harold Pilo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 23:46
CPC Classifications
G; G11; G11C; G11C29/00; G01; G01R; G01R31/00; G01R31/28; G01R31/30
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
258 words
A static random access memory device comprising: a random access memory array having a plurality of memory storage units therein and an address input line, a set input line, a plurality of output data lines and a dummy bit line output; a self reset circuit coupled to the address input line of said array through an address generator; an external clock having an output and an input coupled to said self reset circuit, said external clock emitting an external clock pulse, having a first half and a second half; a set circuit having an input coupled to the dummy bit line output and having first and second outputs, the first output being coupled to the set input line; address generation means for sending a test cycle to said random access memory array; a data latch having first and second inputs and an output, the first input of said data latch being coupled to said memory array output data lines and the second input of said data latch being coupled to the second output of said set circuit; a look aside latch having first, second and third inputs and an output, the first input of said look aside latch being coupled to the first input of said data latch; a device output coupled to the output of the data latch; and feedback means coupling the second output of said set circuit to said self reset circuit to cause said self reset circuit to reset a predetermined number of times during said external clock pulse emitted by said external clock.
Claim 2
Dependent Claim
258 words
A static random access memory device comprising: a random access memory array having a plurality of memory storage units therein and an address input line, a set input line, a plurality of output data lines and a dummy bit line output; a self reset circuit coupled to the address input line of said array through an address generator; an external clock having an output and an input coupled to said self reset circuit, said external clock emitting an external clock pulse, having a first half and a second half; a set circuit having an input coupled to the dummy bit line output and having first and second outputs, the first output being coupled to the set input line; address generation means for sending a test cycle to said random access memory array; a data latch having first and second inputs and an output, the first input of said data latch being coupled to said memory array output data lines and the second input of said data latch being coupled to the second output of said set circuit; a look aside latch having first, second and third inputs and an output, the first input of said look aside latch being coupled to the first input of said data latch; a device output coupled to the output of the data latch; and feedback means coupling the second output of said set circuit to said self reset circuit to cause said self reset circuit to reset a predetermined number of times during said external clock pulse emitted by said external clock.
Claim 3
Dependent Claim
233 words
A static random access memory module comprising: a random access memory array having a plurality of memory storage units therein and an address input line, a set input line, a plurality of output data lines and a dummy bit line output; a self reset circuit coupled to the address input line of said array through an address generator; an external clock having an output coupled to said self reset circuit, said external clock emitting an external clock pulse, having a first half and a second half; a set circuit coupled to the dummy bit line output and having first and second outputs, the first output being coupled to the set input line; address generation means for sending a test cycle to said random access memory array; a data latch having first and second inputs and an output, the first input of said data latch being coupled to said memory array output data lines and the second input of said data latch being coupled to the second output of said set circuit; a module output coupled to the output of the data latch; and feedback means comprising a restore logic circuit coupled to the second output of said set circuit and between said self reset circuit and said external clock output; and a compare latching circuit coupled between the restore logic circuit and the output of said data latch an d said module output.
Claim 4
Dependent Claim
233 words
A static random access memory module comprising: a random access memory array having a plurality of memory storage units therein and an address input line, a set input line, a plurality of output data lines and a dummy bit line output; a self reset circuit coupled to the address input line of said array through an address generator; an external clock having an output coupled to said self reset circuit, said external clock emitting an external clock pulse, having a first half and a second half; a set circuit coupled to the dummy bit line output and having first and second outputs, the first output being coupled to the set input line; address generation means for sending a test cycle to said random access memory array; a data latch having first and second inputs and an output, the first input of said data latch being coupled to said memory array output data lines and the second input of said data latch being coupled to the second output of said set circuit; a module output coupled to the output of the data latch; and feedback means comprising a restore logic circuit coupled to the second output of said set circuit and between said self reset circuit and said external clock output; and a compare latching circuit coupled between the restore logic circuit and the output of said data latch an d said module output.
Claim 5
Dependent Claim
103 words
The module of claim 2 wherein said restore logic circuit comprises a first single output multiplexor circuit having a first, second and third input, coupled between the external clock and said self reset circuit; a single input, single output counter coupled between the first multiplexor circuit and a single output comparator having a first and a second input, and a reset logic circuit having a first and a second output and a first and a second input with said first input coupled to the output of said comparator and the first output being coupled to the first input of said first multiplexor circuit.
Claim 6
Dependent Claim
44 words
The module of claim 3 wherein said output counter is set to a preselected number which is equal to the times the test cycle is to be recycled through the memory array during the first half of said pulse emitted by said external clock.
Claim 7
Dependent Claim
15 words
The module of claim 4 wherein: said preselected number can range between 2 and 32.
Claim 8
Dependent Claim
44 words
The module of claim 3 wherein: said counter is coupled between the output of the first multiplexor circuit and the first input of the comparator, and there is further provided a stop count line from a tester to the second input of the comparator.
Claim 9
Dependent Claim
62 words
The module of claim 4 wherein: there is further provided means for coupling a burn-in multi-mode line from a tester to said second input of the reset logic circuit, and means for coupling the first output of the reset logic circuit to said first multiplexor circuit and for coupling the second output of the reset logic circuit to the compare latching circuit.
Claim 10
Dependent Claim
50 words
The module of claim 3 wherein: the compare latching circuit comprises a three input, single output compare/inverting circuit, a single output look aside latch circuit having a first, a second and a third input and a second single output, multiplexor circuit having a first, a second and a third input.
Claim 11
Dependent Claim
91 words
The module of claim 8 wherein: the output data lines are coupled to the first input of the the look aside latch circuit; the outputs of both the data latch and the look aside latch circuit are coupled to the second single output, three input multiplexor circuit and to selected, respective inputs of the compare/inverting circuit; the output of the compare/inverting circuit is coupled to the second input of the look aside latch circuit; and the output of the second multiplexor circuit is coupled to a single input, single output buffer/latch.
Claim 12
Independent Claim
283 words
A method of testing, for a selected period of time set by an external clock, a random access memory module having a plurality of circuits therein, said circuits including, a random access memory array having a plurality of memory storage units therein and an address input line, a set input line, a plurality of output data lines and a dummy bit line output; a self reset circuit coupled to the address input line of said array through an address generator; the external clock having an output coupled to said self reset circuit; a set circuit coupled to the dummy bit line output and having first and second outputs, the first output being coupled to the set input line; address generation means for sending a test cycle to said random access memory array; and feedback means comprising a restore logic circuit coupled to the second output of said set circuit and between said self reset circuit and said external clock output; and a compare latching circuit coupled between the restore logic circuit and an output of a data latch and a module output comprising the steps of: sending a clock cycle having a first half and a second half, from said external clock to said module; sending data to the module to initiate a test of said module; and feeding a signal from said set circuit through said restore logic circuit to said self reset circuit, to reset said self reset circuit multiple times, during the first half of the clock cycle, to repetitively send the data, through the module multiple times during the first half of the clock cycle to increase the number of times the circuits are stressed during the clock cycle.
Claim 13
Independent Claim
283 words
A method of testing, for a selected period of time set by an external clock, a random access memory module having a plurality of circuits therein, said circuits including, a random access memory array having a plurality of memory storage units therein and an address input line, a set input line, a plurality of output data lines and a dummy bit line output; a self reset circuit coupled to the address input line of said array through an address generator; the external clock having an output coupled to said self reset circuit; a set circuit coupled to the dummy bit line output and having first and second outputs, the first output being coupled to the set input line; address generation means for sending a test cycle to said random access memory array; and feedback means comprising a restore logic circuit coupled to the second output of said set circuit and between said self reset circuit and said external clock output; and a compare latching circuit coupled between the restore logic circuit and an output of a data latch and a module output comprising the steps of: sending a clock cycle having a first half and a second half, from said external clock to said module; sending data to the module to initiate a test of said module; and feeding a signal from said set circuit through said restore logic circuit to said self reset circuit, to reset said self reset circuit multiple times, during the first half of the clock cycle, to repetitively send the data, through the module multiple times during the first half of the clock cycle to increase the number of times the circuits are stressed during the clock cycle.
References Cited (Backward Citations)
US5341096A
Cited
US5327074A
Cited
US5381087A
Cited
US5353254A
Cited
US5467356A
Cited
US5511029A
Cited
US5493532A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-14 | 2003-09-13 | 2004-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-14 | 2007-09-13 | 2008-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-14 | 2011-09-13 | 2012-03-14 | $7700.00 | Window Closed / Lapsed |