Burn-in circuit and burn-in test method

Claim 3

A burn-in test method according to claim 1, wherein said predeteremined pin is a pin to which an address signal is not applied.

Claim 4

A burn-in test method of a semiconductor memory device having a plurality of pins, a memory cell array including first, second, third, to nth word lines, and a plurality of corresponding word line drivers for receiving a row address decoding signal and a reset signal, said method comprising the steps of: generating a burn-in enable signal by applying a voltage greater than an operating voltage of said device to a predetermined pin of said semiconductor; preventing a word line driver reset operation using said burn-in enable signal; enabling a first word line using a first row address synchronized with a first input of a row address strobe signal; enabling a second word line using a second row address synchronized with a second input of said row address strobe signal while said first word line is enabled; enabling a third word line using a third row address synchronized with a third input of said row address strobe signal while said first and second word lines are enabled; and sequentially enabling each increasing word line including said nth word line using a corresponding row address and a subsequent row address strobe signal while still enabling said previously enabled word lines; and continuing to enable all of said word lines for a predetermined time in order to complete said burn-in test.

Claim 5

A burn-in test method of a semiconductor memory device having a plurality of pins, a memory cell array including first, second, third, to nth word lines, and a plurality of corresponding word line drivers for receiving a row address decoding signal and a reset signal, said method comprising the steps of: generating a burn-in enable signal by applying a voltage greater than an operating voltage of said device to a predetermined pin of said semiconductor; preventing a word line driver reset operation using said burn-in enable signal; enabling a first word line using a first row address synchronized with a first input of a row address strobe signal; enabling a second word line using a second row address synchronized with a second input of said row address strobe signal while said first word line is enabled; enabling a third word line using a third row address synchronized with a third input of said row address strobe signal while said first and second word lines are enabled; and sequentially enabling each increasing word line including said nth word line using a corresponding row address and a subsequent row address strobe signal while still enabling said previously enabled word lines; and continuing to enable all of said word lines for a predetermined time in order to complete said burn-in test.

Claim 6

A semiconductor memory device having a plurality of pins, a plurality of word line drivers for each receiving a row address signal synchronized with a row address strobe signal to enable a given word line, and a precharge reset signal to reset said given word line, said device comprising: a memory cell array having a plurality of memory storage locations, each of said plurality of memory storage locations including a memory cell transistor coupled to one of said word lines; a burn-in enable circuit connected to a first pin of said semiconductor memory device for generating a burn-in enable signal of a first voltage level when a voltage greater than an operating voltage of said device is applied to said first pin; and a word line driver reset circuit for resetting said given word line when said precharge reset signal is input, said word line driver reset circuit further inputting a word line driver reset signal that is derived from said row address strobe signal and said burn-in enable signal such that said word line driver reset circuit does not reset said given word line when said word line driver reset signal is present so that a burn-in test of all of said memory cell transistors in said memory cell array can be performed simultaneously while said burn-in enable signal is generated.

Claim 7

A semiconductor memory device having a plurality of pins, a plurality of word line drivers for each receiving a row address signal synchronized with a row address strobe signal to enable a given word line, and a precharge reset signal to reset said given word line, said device comprising: a memory cell array having a plurality of memory storage locations, each of said plurality of memory storage locations including a memory cell transistor coupled to one of said word lines; a burn-in enable circuit connected to a first pin of said semiconductor memory device for generating a burn-in enable signal of a first voltage level when a voltage greater than an operating voltage of said device is applied to said first pin; and a word line driver reset circuit for resetting said given word line when said precharge reset signal is input, said word line driver reset circuit further inputting a word line driver reset signal that is derived from said row address strobe signal and said burn-in enable signal such that said word line driver reset circuit does not reset said given word line when said word line driver reset signal is present so that a burn-in test of all of said memory cell transistors in said memory cell array can be performed simultaneously while said burn-in enable signal is generated.

Claim 8

A semiconductor memory device according to claim 4, wherein said burn-in enable circuit comprises: a CMOS pullup circuit having a pull-up node and having a control terminal connected to a power voltage terminal; a plurality of diodes serially connected between said first pin of said semiconductor memory device and said pull-up node of said CMOS pullup circuit; and a circuit for generating said burn-in enable signal, said circuit for generating being driven by an output of said CMOS pull-up circuit.

Claim 9

A semiconductor memory device according to claim 4, wherein said word line driver reset circuit comprises an OR circuit having a first input connected to a row address master clock signal derived from said row address strobe signal and a second input connected to said burn-in enable signal.

Claim 10

A semiconductor memory device according to claim 5, wherein said word line driver reset circuit comprises an OR circuit having a first input connected to a row address master clock signal derived from said row address strobe signal and a second input connected to said burn-in enable signal.

Claim 11

A semiconductor memory device having a plurality of pins, a plurality of word line drivers for each receiving a row address signal synchronized with a row address strobe signal to enable a given word line, and a precharge reset signal to reset said given word line, said device comprising: a memory cell array having a plurality of memory storage locations, each of said plurality of memory storage locations including a memory cell transistor coupled to one of said word lines; a burn-in enable circuit connected to a first pin of said semiconductor memory device for generating a burn-in enable signal; and a word line driver reset circuit for resetting said given word line when said precharge reset signal is input, said word line driver reset circuit further inputting a word line driver reset signal that is derived from said row address strobe signal and said burn-in enable signal such that said word line driver reset circuit does not reset said given word line when said word line driver reset signal is present so that a burn-in test of all of said memory cell transistors in said memory cell array can be performed simultaneously while said burn-in enable signal is generated.

Claim 12

A semiconductor memory device having a plurality of pins, a plurality of word line drivers for each receiving a row address signal synchronized with a row address strobe signal to enable a given word line, and a precharge reset signal to reset said given word line, said device comprising: a memory cell array having a plurality of memory storage locations, each of said plurality of memory storage locations including a memory cell transistor coupled to one of said word lines; a burn-in enable circuit connected to a first pin of said semiconductor memory device for generating a burn-in enable signal; and a word line driver reset circuit for resetting said given word line when said precharge reset signal is input, said word line driver reset circuit further inputting a word line driver reset signal that is derived from said row address strobe signal and said burn-in enable signal such that said word line driver reset circuit does not reset said given word line when said word line driver reset signal is present so that a burn-in test of all of said memory cell transistors in said memory cell array can be performed simultaneously while said burn-in enable signal is generated.

Claim 13

A semiconductor memory device according to claim 8, wherein said burn-in enable circuit comprises: a CMOS pullup circuit having a pull-up node and having a control terminal connected to a power voltage terminal; a plurality of diodes serially connected between said first pin of said semiconductor memory device and said pull-up node of said CMOS pullup circuit; and a circuit for generating said burn-in enable signal, said circuit for generating being driven by an output of said CMOS pull-up circuit.