US5586332A — Power management for low power processors through…

Claim 1

Independent Claim 156 words

A method for minimizing power consumption of a processing component, comprising the steps of: detecting the execution of a predetermined instruction that during the execution of the instruction the processing component is in a wait state for a length of time at least as long as the time it takes to stop and restart the clocks; stopping the clock signal input to elements of the processing component when the processing component is to enter a wait state during execution of the predetermined instruction, such that certain elements of the processing component do not operate and consume power; detecting the occurrence of a predetermined event indicative that the processing component is to exit the wait state; and restarting the clock signal input to the elements of the processing component when the occurrence of the predetermined event is detected thereby reinitiating operation of the certain elements of the processing component such that the processing component resumes normal operation.

Claim 2

Independent Claim 156 words

A method for minimizing power consumption of a processing component, comprising the steps of: detecting the execution of a predetermined instruction that during the execution of the instruction the processing component is in a wait state for a length of time at least as long as the time it takes to stop and restart the clocks; stopping the clock signal input to elements of the processing component when the processing component is to enter a wait state during execution of the predetermined instruction, such that certain elements of the processing component do not operate and consume power; detecting the occurrence of a predetermined event indicative that the processing component is to exit the wait state; and restarting the clock signal input to the elements of the processing component when the occurrence of the predetermined event is detected thereby reinitiating operation of the certain elements of the processing component such that the processing component resumes normal operation.

Claim 3

Dependent Claim 44 words

The method as set forth in claim 1, wherein the step of detecting the execution of the predetermined instruction comprises the step of monitoring the bus for initiation of predetermined bus cycles determined to cause the processing component to be in a wait state.

Claim 4

Dependent Claim 47 words

The method as set forth in claim 1, wherein the step of detecting the execution of the predetermined instruction comprises the step of monitoring the types of instructions executed by the processing component to identify those instructions which cause the processing component to enter a wait state.

Claim 5

Dependent Claim 45 words

The method as set forth in claim 1, wherein the step of stopping the clock signal input stops the clock signal input to the elements of the processing component which do not detect the occurrence of a predetermined event and restart the clock signal input.

Claim 6

Dependent Claim 41 words

The method as set forth in claim 1, wherein the step of detecting the occurrence of a predetermined event comprises the step of detecting the issuance of a ready signal indicative that data is to be available to the processing component.

Claim 7

Dependent Claim 28 words

The method as set forth in claim 1, wherein the step of detecting the occurrence of a predetermined event detects that data is available to the processing component.

Claim 8

Dependent Claim 31 words

The method as set forth in claim 1, wherein the step of detecting the execution of the predetermined instruction comprises the step of detecting the initiation of I/O read/write bus cycles.

Claim 9

Dependent Claim 32 words

The method as set forth in claim 1, wherein the step of detecting the execution of the predetermined instruction comprises the step of detecting the initiation of non-cacheable memory data read cycles.

Claim 10

Dependent Claim 37 words

The method as set forth in claim 1, wherein the step of detecting the execution of the predetermined instruction comprises the step of detecting the initiation of the first memory data read of a cache line fill.

Claim 11

Dependent Claim 32 words

The method as set forth in claim 1, wherein the step of detecting the execution of the predetermined instruction comprises the step of detecting the initiation of processing component specific bus cycles.

Claim 12

Dependent Claim 32 words

The method as set forth in claim 1, wherein the step of detecting the execution of the predetermined instruction comprises the step of detecting processing component stalls during external memory write cycles.

Claim 13

Dependent Claim 44 words

The method as set forth in claim 11, wherein the step of detecting comprises the steps of: determining that a write buffer is full, detecting that the external bus is busy with a bus cycle, and the instruction executing issues a memory write cycle.

Claim 14

Dependent Claim 59 words

The method as set forth in claim 1, further comprising the step of confirming that a coprocessor is not busy and a cache invalidation bus cycle is not in progress prior to stopping the clock signal input, such that if the coprocessor is busy or a cache invalidation cycle is in progress, the clock signal input is not stopped.

Claim 15

Dependent Claim 136 words

A processing component comprising: means for executing instructions, said means receiving a clock signal input to drive the means for executing instructions; means for detecting the execution of a predetermined instruction, said means for executing waiting during at least a portion of the time required to execute the predetermined instruction; means for stopping the clock signal input to drive the means for executing instructions when the means for executing instructions is to wait during execution of the predetermined instruction; means for detecting the occurrence of a predetermined event indicative that the processing component is to cease waiting; and means for restarting the clock signal input to the processing component when the occurrence of the predetermined event is detected thereby reinitiating the operation of the means for executing instructions such that the processing component resumes normal operation.

Claim 16

Dependent Claim 136 words

A processing component comprising: means for executing instructions, said means receiving a clock signal input to drive the means for executing instructions; means for detecting the execution of a predetermined instruction, said means for executing waiting during at least a portion of the time required to execute the predetermined instruction; means for stopping the clock signal input to drive the means for executing instructions when the means for executing instructions is to wait during execution of the predetermined instruction; means for detecting the occurrence of a predetermined event indicative that the processing component is to cease waiting; and means for restarting the clock signal input to the processing component when the occurrence of the predetermined event is detected thereby reinitiating the operation of the means for executing instructions such that the processing component resumes normal operation.

Claim 17

Dependent Claim 61 words

The processing component as set forth in claim 14, wherein execution of the predetermined instruction causes bus cycles to be initiated by the processing component, said means for detecting the execution of the predetermined instruction comprises bus monitoring means which detects the initiation of predetermined bus cycles which are determined to cause the processing component to be in a wait state.

Claim 18

Dependent Claim 58 words

The processing component as set forth in claim 14, wherein the means for detecting the execution of the predetermined instruction comprises microcode which monitors the types of instructions executed by the processing component to identify those instructions which cause the processing component to enter a wait state and determines when the means for executing enters a wait state.

Claim 19

Dependent Claim 41 words

The processing component as set forth in claim 14, wherein the means for detecting the occurrence of a predetermined event comprises means for detecting the receipt of a ready signal indicative that data is to be available to the processing component.

Claim 20

Dependent Claim 32 words

The processing component as set forth in claim 14, wherein the means for detecting the occurrence of a predetermined event detects that data is available to be received by the processing component.

Claim 21

Dependent Claim 56 words

The processing component as set forth in claim 14, further comprising a write buffer for writing data to be written to external memory and an external bus connecting the processing component and external memory, said means for detecting the execution of the predetermined instruction comprising, means for detecting processing component stalls during external memory write cycles.

Claim 22

Dependent Claim 51 words

The processing component as set forth in claim 19, wherein the means for detecting processing component stalls comprises: means for determining that a write buffer is full, means for detecting that the external bus is busy with a bus cycle; and means for detecting the issuance of a memory write cycle.

Claim 23

Dependent Claim 60 words

The processing component as set forth in claim 14, further comprising a means for confirming that a coprocessor is not busy and a cache invalidation bus cycle is not in progress prior to stopping the clock signal input, such that if the coprocessor is busy or a cache invalidation cycle is in progress, the clock signal input is not stopped.

Claim 24

Dependent Claim 153 words

A processor comprising: a central processing unit for executing instructions, said CPU receiving a CPU clock signal input to drive the CPU; a clock controller coupled to receive at least one clock signal and output the CPU clock signal, said controller comprising; a first detector for detecting the execution of a predetermined instruction, said CPU waiting during at least a portion of the time required to execute the predetermined instruction, logic responsive to the first detector for stopping the CPU clock signal input when the CPU is to wait during execution of the predetermined instruction, a second detector which detects the occurrence of a predetermined event indicative that the CPU is to cease waiting, and logic responsive to the second detector for restarting the clock signal input to the processor when the occurrence of the predetermined event is detected thereby reinitiating the operation of the CPU such that the processor resumes normal operation.

Claim 25

Dependent Claim 153 words

A processor comprising: a central processing unit for executing instructions, said CPU receiving a CPU clock signal input to drive the CPU; a clock controller coupled to receive at least one clock signal and output the CPU clock signal, said controller comprising; a first detector for detecting the execution of a predetermined instruction, said CPU waiting during at least a portion of the time required to execute the predetermined instruction, logic responsive to the first detector for stopping the CPU clock signal input when the CPU is to wait during execution of the predetermined instruction, a second detector which detects the occurrence of a predetermined event indicative that the CPU is to cease waiting, and logic responsive to the second detector for restarting the clock signal input to the processor when the occurrence of the predetermined event is detected thereby reinitiating the operation of the CPU such that the processor resumes normal operation.

Claim 26

Dependent Claim 28 words

The processor as set forth in claim 22, said clock controller generating a second CPU clock signal, said second CPU clock signal being maintained in an on state.

Claim 27

Dependent Claim 46 words

The processor as set forth in claim 22, wherein the first detector comprises microcode which monitors the types of instructions executed by the CPU to identify those instructions which cause the CPU to enter a wait state and determines when the CPU enters a wait state.

Claim 28

Dependent Claim 36 words

The processor as set forth in claim 22, wherein the first detector comprises logic coupled to monitor bus cycles initiated by the CPU which are determined to cause the CPU to be in a wait state.

Claim 29

Dependent Claim 29 words

The processor as set forth in claim 22, wherein the second detector is coupled to receive a ready signal indicative that data is to be available to the processor.

Claim 30

Dependent Claim 23 words

The processor as set forth in claim 22, wherein the second detector detects that data is available to be received by the processor.

Claim 31

Dependent Claim 43 words

The processor as set forth in claim 22, further comprising a write buffer for writing data to be written to external memory and an external bus connecting the processor and external memory, said first detector detecting processor stalls during external memory write cycles.

Claim 32

Dependent Claim 38 words

The processor as set forth in claim 28, said first detector: determining that a write buffer is full; detecting that the external bus is busy with a bus cycle; and detecting the issuance of a memory write cycle.

Claim 33

Dependent Claim 58 words

The processor as set forth in claim 22, further comprising logic for confirming that a coprocessor is not busy and a cache invalidation bus cycle is not in progress prior to stopping the clock signal input, such that if the coprocessor is busy or a cache invalidation cycle is in progress, the clock signal input is not stopped.

Claim 34

Dependent Claim 200 words

A microprocessor system comprising: a bus; a central processing unit (CPU) coupled to the bus, said CPU receiving a CPU clock signal input to drive the CPU, said CPU initiating bus cycles on the bus to communicate information with a device, said CPU entering a wait state during the execution of a predetermined instruction comprising communications with the device across the bus; at least one device coupled to the bus, said device receiving signals indicative of the bus cycle initiated by the CPU and subsequently issuing signals on the bus to the CPU indicative of a response to bus cycle signals received and; a clock controller which controls the CPU clock signal input, said clock controller coupled to the bus detecting the execution of the predetermined instruction and stopping the CPU clock signal when the CPU enters a wait state, said CPU monitoring the bus for issuance of bus cycle signals by the device, said clock controller restarting the CPU clock signal when the device issued bus cycle signals are detected such that the CPU begins normal operation; wherein power consumption by the CPU is minimized by stopping the clock when the CPU would be operating in a wait state.

Claim 35

Dependent Claim 200 words

A microprocessor system comprising: a bus; a central processing unit (CPU) coupled to the bus, said CPU receiving a CPU clock signal input to drive the CPU, said CPU initiating bus cycles on the bus to communicate information with a device, said CPU entering a wait state during the execution of a predetermined instruction comprising communications with the device across the bus; at least one device coupled to the bus, said device receiving signals indicative of the bus cycle initiated by the CPU and subsequently issuing signals on the bus to the CPU indicative of a response to bus cycle signals received and; a clock controller which controls the CPU clock signal input, said clock controller coupled to the bus detecting the execution of the predetermined instruction and stopping the CPU clock signal when the CPU enters a wait state, said CPU monitoring the bus for issuance of bus cycle signals by the device, said clock controller restarting the CPU clock signal when the device issued bus cycle signals are detected such that the CPU begins normal operation; wherein power consumption by the CPU is minimized by stopping the clock when the CPU would be operating in a wait state.

Claim 36

Dependent Claim 36 words

The system as set forth in claim 31, said clock controller further coupled to receive a second clock signal input which drives the clock controller, said second clock signal input being maintained in an on state.

Claim 37

Dependent Claim 18 words

The system as set forth in claim 31 wherein said clock controller is located on the CPU component.

Claim 38

Dependent Claim 18 words

The system as set forth in claim 31, wherein said clock controller is located external to the CPU.

Claim 39

Dependent Claim 46 words

The system as set forth in claim 31, wherein said clock controller comprises microcode which monitors the types of instructions executed by the CPU to identify those instructions which cause the CPU to enter a wait state and determines when the CPU enters a wait state.

Claim 40

Dependent Claim 37 words

The system as set forth in claim 31, wherein the clock controller comprises logic coupled to monitor bus cycles initiated by the CPU which are determined to cause the CPU to be placed in a wait state.

Claim 41

Dependent Claim 36 words

The system as set forth in claim 31, wherein the bus signal issued by the device comprises a ready signal indicative that data is to be placed on the bus to be available to the processor.

Claim 42

Dependent Claim 32 words

The system as set forth in claim 31, wherein the bus signal also issued by the device comprises data placed on the bus to be available to be received by the processor.

Claim 43

Dependent Claim 17 words

The system as set forth in claim 31, wherein the predetermined instruction comprises I/O read/write bus cycles.

Claim 44

Dependent Claim 18 words

The system as set forth in claim 31, wherein the predetermined instruction comprises non-cacheable memory data read cycles.

Claim 45

Dependent Claim 24 words

The system as set forth in claim 31, wherein the predetermined instruction comprises a first memory data read cycle of a cache line fill.

Claim 46

Dependent Claim 40 words

The system as set forth in claim 31, further comprising external memory coupled to the bus and a write buffer for writing data to be written to external memory, said clock controller detecting processor stalls during external memory write cycles.

Claim 47

Dependent Claim 39 words

The system as set forth in claim 42, wherein said clock controller; determining that a write buffer is full; detecting that the external bus is busy with a bus cycle; and detecting the issuance of a memory write cycle.

Claim 48

Dependent Claim 45 words

The system as set forth in claim 31, wherein said clock controller stops the CPU clock signal when the CPU enters a wait state and a coprocessor is confirmed not to be busy performing operations and a cache invalidation bus cycle is not in progress.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1999-12-17	2000-06-17	2000-12-17	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2003-12-17	2004-06-17	2004-12-17	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2007-12-17	2008-06-17	2008-12-17	$7700.00	Window Closed / Lapsed

Power management for low power processors through the use of auto clock-throttling

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag