US4639864A
Expired / Lapsed
US
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Power interlock system and method for use with multiprocessor systems
Assignee: TCI-DELAWARE INCORPORATED A CORP OF DEL
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Filing: 1980-05-06
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Granted: 1987-01-27
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Expires: 2000-05-06
Abstract
Abstract A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing. The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. The multiprocessor system includes a distributed power supply system which insures non-stop operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. A power interlock system and a method are provided for protection against data corruption.
Inventors
- 👤 James A. Katzman
- 👤 Joel F. Bartlett
- 👤 Richard M. Bixler
- 👤 William H. Davidow
- 👤 John A. Despotakis
- 👤 Peter J. Graziano
- 👤 Michael D. Green
- 👤 David A. Greig
- 👤 Steven J. Hayashi
- 👤 David R. Mackie
- 👤 Dennis L. McEvoy
- 👤 James G. Treybig
- 👤 Steven W. Wierenga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:59
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/76; G06F7/78; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1044; G06F11/16; G06F11/20; G06F11/2002; G06F11/2007; G06F11/2015; G06F11/202; G06F11/2023; G06F11/2035; G06F11/2043; G06F11/2097; G06F12/00; G06F12/02; G06F12/08; G06F12/14; G06F12/1458; G06F13/00; G06F13/10; G06F13/12; G06F13/122; G06F13/14; G06F13/20; G06F13/28; G06F13/287; G06F13/36; G06F13/362; G06F13/366; G06F13/38; G06F15/00; G06F15/16; G06F15/163; G06F15/167; G06F15/173; G06F5/00; G06F5/06
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
139 words
A power interlock system for preventing corruption of data on a bus by isolating from the bus logic modules which are usually connected thereto comprising a plurality of logic modules including interface logic, a bus connected to the logic modules for communicating data therebetween, power supply means for supplying power to the logic modules, voltage monitor means for detecting whether the voltage supplied by the power supply is within a safe power-on range, a safe power-off range, and an unsafe intermediate range, the interface logic being responsive to the voltage monitor means for operatively isolating a logic module from the bus to prevent corruption of data on the bus when the voltage supplied to that logic module is in the power-off range or the intermediate range by causing the logic module is present a high impedance to the bus.
Claim 2
Dependent Claim
139 words
A power interlock system for preventing corruption of data on a bus by isolating from the bus logic modules which are usually connected thereto comprising a plurality of logic modules including interface logic, a bus connected to the logic modules for communicating data therebetween, power supply means for supplying power to the logic modules, voltage monitor means for detecting whether the voltage supplied by the power supply is within a safe power-on range, a safe power-off range, and an unsafe intermediate range, the interface logic being responsive to the voltage monitor means for operatively isolating a logic module from the bus to prevent corruption of data on the bus when the voltage supplied to that logic module is in the power-off range or the intermediate range by causing the logic module is present a high impedance to the bus.
Claim 3
Dependent Claim
34 words
The invention of claim 1 wherein the interface logic further includes means for causing the interface logic to present a low impedance to the bus for operatively connecting a logic module to the bus.
Claim 4
Dependent Claim
146 words
A power interlock system for preventing corruption of data on a bus by isolating from the bus logic modules which are normally connected thereto comprising a plurality of logic modules each including interface logic and voltage monitor means, a bus connected to the logic modules for communicating data therebetween, and power supply means for supplying power to the logic modules, the voltage monitor means for detecting whether the voltage supplied by the power supply is within a safe power-on range, a safe power-off range, or an unsafe intermediate range, the interface logic being responsive to the voltage monitor means for operatively isolating a logic module from the bus to prevent corruption of data on the bus when the voltage supplied to that logic module is in the power-off range or the intermediate range by causing the logic module to present a high impedance to the bus.
Claim 5
Dependent Claim
146 words
A power interlock system for preventing corruption of data on a bus by isolating from the bus logic modules which are normally connected thereto comprising a plurality of logic modules each including interface logic and voltage monitor means, a bus connected to the logic modules for communicating data therebetween, and power supply means for supplying power to the logic modules, the voltage monitor means for detecting whether the voltage supplied by the power supply is within a safe power-on range, a safe power-off range, or an unsafe intermediate range, the interface logic being responsive to the voltage monitor means for operatively isolating a logic module from the bus to prevent corruption of data on the bus when the voltage supplied to that logic module is in the power-off range or the intermediate range by causing the logic module to present a high impedance to the bus.
Claim 6
Independent Claim
114 words
A method for preventing corruption of data on a bus in systems wherein a bus interconnects a plurality of logic modules comprising the steps of supplying power to the logic modules, monitoring the voltage supplied to the logic modules by the power supply to determine whether the voltage is within a safe power on range, a safe power off range, or an unsafe intermediate range, and operatively isolating a logic module from the bus when the monitored voltage for that module is in the power off range or the intermediate range before corruption of any data on the bus can occur by causing the logic module to present a high impedance to the bus.
Claim 7
Independent Claim
114 words
A method for preventing corruption of data on a bus in systems wherein a bus interconnects a plurality of logic modules comprising the steps of supplying power to the logic modules, monitoring the voltage supplied to the logic modules by the power supply to determine whether the voltage is within a safe power on range, a safe power off range, or an unsafe intermediate range, and operatively isolating a logic module from the bus when the monitored voltage for that module is in the power off range or the intermediate range before corruption of any data on the bus can occur by causing the logic module to present a high impedance to the bus.
Claim 8
Dependent Claim
45 words
The method of claim 4 wherein the isolating step includes the step of causing the logic module to present a low impedance to the bus when the monitored voltage is in the power on range and the logic module is transmitting data on the bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-26 | 1990-07-28 | 1991-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-26 | 1994-07-28 | 1995-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-26 | 1998-07-28 | 1999-01-27 | $7700.00 | Window Closed / Lapsed |