Analog autonomous test bus framework for testing integrated circuits on a printed circuit board

Claim 2

An analog integrated circuit chip with incorporated testing means comprising (a) a core circuit, said core circuit having at least one input and at least one output internal to the chip, (b) pins for coupling externally to the chip, (c) at least a first switching cell, said switching cell having a first input, a control second input, an output, and a bidirectional test port, (d) first means for coupling the switching cell first input to a first pin, (e) second means for coupling the switching cell second input to a second pin, (f) third means for coupling the switching cell output to a core circuit input, (g) fourth means for coupling the switching cell test port to a third pin, (h) said switching cell, in response to signals received on the second pin, being placeable into one of plural states including a first state, a second state, and a third state; when placed in its first state said switching cell coupling its first input to its output to form a normal path to the core circuit, when placed in its second state said switching cell coupling its test port to its output to form a test input path for the core circuit, and when placed in its third state said switching cell coupling its first input to its test port to form a test output path.

Claim 3

The integrated circuit of claim 1, further comprising a second switching cell coupled between an output of the core circuit and additional pins of the packaged integrated circuit chip, said second switching cell having a first input, a control second input, an output, and a bidirectional test port, said second switching cell in response to signals received on one of the pins being placeable into one of plural states including a first state, a second state, and a third state; when placed into said first state said second switching cell coupling its first input to its output to form a normal path from the core circuit, when placed in its second state said switching cell coupling its test port to its output to form a test output path from the test port, when placed in its third state said switching cell coupling its first input to its test port to form a test output path from the core circuit.

Claim 4

A system comprising first and second integrated circuits each comprising the testing means as claimed in claim 2, wherein said integrated circuits each comprise a fourth pin coupled with the output of the core circuit, the system further comprising additional circuitry for coupling the first and second integrated circuits via their first and fourth pins, respectively, and means for applying control signals to second pins of the first and second integrated circuits to establish a testing circuit for the additional circuitry.

Claim 5

The system of claim 3, further comprising a test bus and a data bus, means for coupling the second pins of the first and second integrated circuits with the data bus, and means for coupling the third pins of the first and second integrated circuits with the test bus.

Claim 6

An analog integrated circuit chip with incorporated testing means comprising (a) a core circuit, said core circuit having at least one input and at least one output internal to the chip, (b) pins for coupling externally to the chip, (c) at least a first switching cell, said switching cell having a first input, a control second input, an output, and a bidirectional test port, (d) first means for coupling the switching cell first input to a core circuit output, (e) second means for coupling the switching cell second input to a second pin, (f) third means for coupling the switching cell output to a first pin, (g) fourth means for coupling the switching cell test port to a third pin, (h) said switching cell, in response to signals received on the second pin, being placeable into one of plural states including a first state, a second state, and a third state, when placed in its first state said switching cell coupling its first input to its output to form a normal path from the core circuit; when placed in its second state said switching cell coupling its test port to its output to form a test output path for the core circuit, and when placed in its third state said switching cell coupling its first input to its test port to form a test output path.

Claim 7

An analog integrated circuit chip with incorporated testing means comprising (a) a core circuit, said core circuit having at least one input and at least one output internal to the chip, (b) pins for coupling externally to the chip, (c) at least a first switching cell, said switching cell having a first input, a control second input, an output, and a bidirectional test port, (d) first means for coupling the switching cell first input to a core circuit output, (e) second means for coupling the switching cell second input to a second pin, (f) third means for coupling the switching cell output to a first pin, (g) fourth means for coupling the switching cell test port to a third pin, (h) said switching cell, in response to signals received on the second pin, being placeable into one of plural states including a first state, a second state, and a third state, when placed in its first state said switching cell coupling its first input to its output to form a normal path from the core circuit; when placed in its second state said switching cell coupling its test port to its output to form a test output path for the core circuit, and when placed in its third state said switching cell coupling its first input to its test port to form a test output path.

Claim 8

Integrated circuit chip comprising an analog core circuit which needs to be analog tested, the core circuit having a multiplicity of normal, non-test connections; a multiplicity of pins; a multiplicity of switching cells arranged in boundary scan fashion around the core circuit, each switching cell being connected between a respective one of the normal, non-test connections of the core circuit and a respective pin; and control means for causing each switching cell to assume a plurality of transmission states, the transmission states including: a first state for switching data between the core circuit and a pin for connecting to a test bus; a second state for switching data between the respective one of the normal, non-test connections of the core circuit and the respective pin; and a third state for switching data between the respective pin and the pin for connecting to the test bus.

Claim 9

Integrated circuit chip comprising an analog core circuit which needs to be analog tested, the core circuit having a multiplicity of normal, non-test connections; a multiplicity of pins; a multiplicity of switching cells arranged in boundary scan fashion around the core circuit, each switching cell being connected between a respective one of the normal, non-test connections of the core circuit and a respective pin; and control means for causing each switching cell to assume a plurality of transmission states, the transmission states including: a first state for switching data between the core circuit and a pin for connecting to a test bus; a second state for switching data between the respective one of the normal, non-test connections of the core circuit and the respective pin; and a third state for switching data between the respective pin and the pin for connecting to the test bus.

Claim 10

A system comprising a plurality of chips as claimed in claim 6; at least one glue circuit or wire for coupling the chips together; at least one bi-directional test bus, wherein the third state of at least one of the switching cells is usable to test the glue circuit.