π/4 quadrature phase shift keying modulator

Claim 2

A π/4 shift quadrature phase shift keying modulator comprising: pre-processing means for subjecting an input transmitting code sequence to a pre-processing; modulator means, coupled to said pre-processing means, for alternately subjecting the transmitting code sequence received via said pre-processing means to a modulation in conformance with a quadrature phase shift keying and a modulation in conformance with a π/4 shift quadrature phase shift keying; and output means, coupled to said modulator means, for outputting a modulated signal in a form of a burst signal based on an output of said modulator means, said pre-processing means carrying out the pre-processing so that I-axis and Q-axis data, supplied to said modulator means from said pre-processing means, have an identical symbol in succession at parts corresponding to leading and trailing edges of the burst signal, so as to suppress generation of unwanted waves in said output means.

Claim 3

The π/4 shift quadrature phase shift keying modulator as claimed in claim 1, wherein said output means includes switching means for turning the output of said modulator means ON/OFF responsive to the burst.

Claim 4

The π/4 shift quadrature phase shift keying modulator as claimed in claim 1, wherein said pre-processing means includes converter means for converting the input transmitting code sequence to parallel transmitting codes a predetermined amount at a time.

Claim 5

The π/4 shift quadrature phase shift keying modulator as claimed in claim 3, wherein said pre-processing means further includes: a first circuit, coupled to said converter means, detecting timings of the leading and trailing edges of the burst signal; and a second circuit, coupled to said first circuit, carrying out a logical operation on the transmitting codes so that the transmitting codes are converted into values such that the I-axis and Q-axis data supplied to said modulator means from said pre-processing means have same symbol in succession at parts corresponding to the leading and trailing edges of the burst signal.

Claim 6

The π/4 shift quadrature phase shift keying modulator as claimed in claim 3, wherein said modulator means includes: an operation part, coupled to said converter means, carrying out a predetermined operation on the transmitting codes received from said converter means and I-axis and Q-axis data of a signal point arrangement of one timing before received from said pre-processing means, so as to obtain the I-axis and Q-axis data of a signal point arrangement of a present timing which is shifted by π/4 from the signal point arrangement of one timing before; converter part, coupled to said operation part, converting the I-axis and Q-axis data of the signal point arrangement of the present timing obtained from said operation part into analog baseband modulating signals of I-channel and Q-channel; and 4-phase phase modulator, coupled to said converter part, subjecting the I-channel and Q-channel baseband modulating signals from said converter part to a 4-phase phase modulation to output the output of said modulator means.

Claim 7

The π/4 shift quadrature phase shift keying modulator as claimed in claim 5, wherein said pre-processing means includes a circuit generating an odd/even judging signal (OE) which is "1" for a normal signal point arrangement of the quadrature phase shift keying and "0" for π/4 shift signal point arrangement of the π/4 shift quadrature phase shift keying.

Claim 8

The π/4 shift quadrature phase shift keying modulator as claimed in claim 6, wherein said operation part includes a circuit obtaining the signal point arrangement of the present timing based on the following Table, and said pre-processing means includes a circuit carrying out a process on the transmitting codes such that a transmitting code (X K , Y K ) is set to (0, 0) if the odd/even judging signal (OE) is "1" in the Table and the transmitting code (X K , Y K ) is set to (1, 0) if the odd/even judging signal (OE) is "0" in the Table, where (I K , Q K ) denotes the I-axis and Q-axis data of the present timing, (*I K , *Q K ) denotes inverted data of (I K , Q K ), (I K-1 , Q K-1 ) denotes the I-axis and Q-axis data of one timing before, and (*I K-1 , *Q K-1 ) denotes inverted data of (I K-1 , Q K-1 ). TABLE __________________________________________________________________________ (X.sub.K, Y.sub.K) +π/4 3π/4 -3π/4 -π/4 (OE, I.sub.K-1, Q.sub.K-1) 0 0 0 1 1 1 1 0 __________________________________________________________________________ 0 I.sub.K-1 Q.sub.K-1 1, I.sub.K-1, Q.sub.K-1 1, *Q.sub.K-1, I.sub.K-1 1, *I.sub.K-1 *Q.sub.K-1 1, Q.sub.K-1, *I.sub.K-1 1 I.sub.K-1 Q.sub.K-1 0, *Q.sub.K-1, I.sub.K-1 0, *I.sub.K-1, *Q.sub.K-1 0, Q.sub.K-1 *I.sub.K-1 0, I.sub.K-1, Q.sub.K-1 __________________________________________________________________________

Claim 9

The π /4 shift quadrature phase shift keying modulator as claimed in claim 7, wherein said pre-processing means further includes: a first circuit, coupled to said converter means, detecting timings of the leading and trailing edges of the burst signal; and a second circuit, coupled to said first circuit, carrying out a logical operation on the transmitting code (X K , Y K ) based on the odd/even judging signal (OE) so that the transmitting code (X K , Y K ) is converted into values such that the I-axis and Q-axis data supplied to said modulator means have the identical symbol in succession at parts corresponding to the leading and trailing edges of the burst signal.

Claim 10

The π/4 shift quadrature phase shift keying modulator as claimed in claim 1, wherein said pre-processing means carries out the pre-processing so that the identical symbol continues in succession at least twice for I-axis and Q-axis data at parts corresponding to the leading and trailing edges of the burst signal.