US5210775A
Expired / Lapsed
US
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π/4 shift QPSK modulator and communication apparatus
Assignee: Hitachi Ltd
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Filing: 1991-02-12
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Granted: 1993-05-11
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Expires: 2011-02-12
Abstract
Abstract A pi /4 shift QPSK modulator for receiving digital signals and for outputting a modulated signal therefrom in accordance with each of the inputted digital signals. The pi /4 QPSK modulator is utilized in a communication apparatus and includes a counter for counting the number of the inputted digital signals, a phase information arithmetic unit for receiving a value of an output from the counter and a value of each of the inputted digital signals for outputting phase information of the signal to be modulated, an arithmetic unit for performing an arithmetic operation on values representing an impulse response of the output phase information from the phase information arithmetic unit and outputting impulse response values in accordance therewith, and an accumulating unit for accumulating impulse response values outputted from the arithmetic unit and for performing an arithmetic operation for enabling generation of a pi /4 shift QPSK modulated signal.
Inventors
- 👤 Yasuaki Takahara
- 👤 Tomohiro Ezaki
- 👤 Shigeyuki Sudo
- 👤 Teiji Okamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 04:51
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/20; H04L27/2032; H04L27/2092
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
133 words
A π/4 shift QPSK modulator for receiving digital signals and for outputting a modulated signal therefrom in accordance with each of the inputted digital signals, comprising: counting means for counting the number of the inputted digital signals; phase information arithmetic means for receiving a value of an output from the counting means and a value of each of the inputted digital signals for outputting phase information of the signal to be modulated; arithmetic means for performing an arithmetic operation on values representing an impulse response of the output phase information from the phase information arithmetic means and outputting impulse response values in accordance therewith; and accumulating means for accumulating impulse response values outputted from the arithmetic means and for performing an arithmetic operation for enabling generation of a π/4 shift QPSK modulated signal.
Claim 2
Dependent Claim
133 words
A π/4 shift QPSK modulator for receiving digital signals and for outputting a modulated signal therefrom in accordance with each of the inputted digital signals, comprising: counting means for counting the number of the inputted digital signals; phase information arithmetic means for receiving a value of an output from the counting means and a value of each of the inputted digital signals for outputting phase information of the signal to be modulated; arithmetic means for performing an arithmetic operation on values representing an impulse response of the output phase information from the phase information arithmetic means and outputting impulse response values in accordance therewith; and accumulating means for accumulating impulse response values outputted from the arithmetic means and for performing an arithmetic operation for enabling generation of a π/4 shift QPSK modulated signal.
Claim 3
Dependent Claim
31 words
A π/4 shift QPSK modulator according to claim 1, further comprising filter means responsive to an output of the accumulating means for enabling generation of the π/4 shift QPSK modulated signal.
Claim 4
Dependent Claim
31 words
A π/4 shift QPSK modulator according to claim 1, further comprising means for receiving the inputted digital signals and selecting a value thereof for application to the phase information arithmetic means.
Claim 5
Dependent Claim
47 words
A π/4 shift QPSK modulator according to claim 3, wherein the receiving means includes shift register means for receiving the input digital signals and providing outputs thereof, and selector means for selecting a value of the shift register means for application to the phase information arithmetic means.
Claim 6
Dependent Claim
82 words
A π/4 shift QPSK modulator according to claim 4, further comprising timing means coupled at least to the shift register means and counting means, the counting means including a bit counter coupled to the phase information arithmetic means, a tap counter coupled to the selector means, the phase information arithmetic means, the arithmetic means and the accumulating means, and an over-sampling counter coupled to the arithmetic means and the accumulating means, and filter means coupled to an output of the accumulating means.
Claim 7
Dependent Claim
35 words
A π/4 shift QPSK modulator according to claim 1, further comprising means for selecting output phase information from the phase information arithmetic means and for supplying the selected output phase information to the arithmetic means.
Claim 8
Dependent Claim
54 words
A π/4 shift QPSK modulator according to claim 6, wherein the selecting means includes shift register means for receiving output phase information from the phase information arithmetic means and providing an output indicative thereof and a selector for selecting at least one output from the shift register means for supply to the arithmetic means.
Claim 9
Dependent Claim
45 words
A π/4 shift QPSK modulator according to claim 1, wherein the phase information arithmetic means comprises storage means and address arithmetic means for performing an arithmetic operation on address information in the storage means in accordance with information received by the phase information arithmetic means.
Claim 10
Dependent Claim
16 words
A π/4 shift QPSK modulator according to claim 1, wherein the arithmetic means includes a ROM.
Claim 11
Dependent Claim
65 words
A π/4 shift QPSK modulator according to claim 1, wherein the arithmetic means includes storage means and numeric converting means for one of performing code inversion on a result of an arithmetic operation outputted by the storage means and converting the result of the arithmetic operation outputted by the storage means into a preset value in accordance with a signal received by the arithmetic means.
Claim 12
Dependent Claim
42 words
A π/4 shift QPSK modulator according to claim 1, further comprising control signal receiving means for receiving a control signal from a control signal generating means, and a counting control means for resetting the counting means in accordance with the control signal.
Claim 13
Dependent Claim
51 words
A π/4 shift QPSK modulator according to claim 1, further comprising first storage means for storing control information and output control means for controlling one of an output level and off-set level of an output of the accumulation means in accordance with the control information stored in the first storage means.
Claim 14
Dependent Claim
96 words
A π/4 shift QPSK modulator according to claim 12, wherein the output control means includes second storage means for storing a series of control information which has been preset, reading means for sequentially reading the control information from the second storage means, and control switching means for performing switching on one of control of the reading means in accordance with the control information stored in the first storage means and control of the reading means in accordance with the control information read from the second storage means and for controlling the operation of the reading means.
Claim 15
Dependent Claim
32 words
A communication apparatus comprising the π/4 shift QPSK modulator according to claim 1, the communication apparatus including means for at least one of transmitting and receiving the π/4 shift QPSK modulated signal.
Claim 16
Dependent Claim
47 words
A communication apparatus comprising the π/4 shift QPSK modulator according to claim 2, the communication apparatus including means for at least one of transmitting and receiving the π/4 shift QPSK modulated signal, the transmitting means including quadrature modulator means coupled to the output of the filter means.
References Cited (Backward Citations)
US4327439A
Cited
US4962510A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-10 | 1996-11-09 | 1997-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-10 | 2000-11-09 | 2001-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-10 | 2004-11-09 | 2005-05-11 | $7700.00 | Window Closed / Lapsed |