Method and apparatus for detecting velocity profiles of a spinning rotor of a polyphase DC motor

Claim 2

A circuit for operating a polyphase dc motor having a plurality of driving coils that are commutatively energized in a predetermined sequence to rotate a rotor, comprising: a zero crossing detector connected to determine when a back emf of a floating driving coil crosses zero; a generator for generating commutation sequence signals for controlling which of said driving coils are energized a delayed time after said zero crossing detector detects that a back emf of a floating driving coil has crossed zero; and mask circuit for inhibiting said zero crossing detector for a delayed time after a commutation change, in dependence upon an acceleration of the rotor, comprising: a period counter, an acceleration counter, and a mask counter, said period counter being an up counter, and said acceleration and mask counters being down counters; a source of clock pulses connected to clock said period and acceleration counters; a programmable clock pulse divider connected to receive and programmably divide said clock pulses to provide clock pulses at a selectively divided frequency to said mask counter; means operative when said zero crossing is detected to load a count from said period counter into said mask and acceleration counters and then to reset said period counter; and an output from said acceleration counter being connected to determine the selectively divided frequency of clock pulses provided by said programmable clock pulse divider to said mask counter.

Claim 3

The circuit of claim 1 further comprising a memory containing a look-up table connected to receive an output of said acceleration counter to provide an output to said programmable clock pulse divider in accordance with said output of said acceleration counter.

Claim 4

A circuit for operating a polyphase dc motor having a plurality of driving coils that are commutatively energized in a predetermined sequence to rotate a rotor, comprising: a commutation sequence generator for generating commutation sequence signals for controlling which of said plurality of driving coils are energized a delayed time after a back emf of a floating one of said coils crosses zero; a period counter, an acceleration counter, and a delay counter, said period counter being an up counter, and said acceleration and delay counters being down counters; a source of clock pulses connected to clock said period and acceleration counters; a programmable clock pulse divider connected to receive and divide said clock pulses to provide clock pulses at a selectively divided frequency to said delay counter; and a circuit operative when said zero crossing is detected to load a count from said period counter into said delay and acceleration counters and then to reset said period counter; an output from said acceleration counter being connected to programmably determine the frequency of clock pulses provided by said programmable clock pulse divider to said delay counter.

Claim 5

A circuit for operating a polyphase dc motor having a plurality of driving coils that are commutatively energized in a predetermined sequence to rotate a rotor, comprising: a commutation sequence generator for generating commutation sequence signals for controlling which of said plurality of driving coils are energized a delayed time after a back emf of a floating one of said coils crosses zero; a period counter, an acceleration counter, and a delay counter, said period counter being an up counter, and said acceleration and delay counters being down counters; a source of clock pulses connected to clock said period and acceleration counters; a programmable clock pulse divider connected to receive and divide said clock pulses to provide clock pulses at a selectively divided frequency to said delay counter; and a circuit operative when said zero crossing is detected to load a count from said period counter into said delay and acceleration counters and then to reset said period counter; an output from said acceleration counter being connected to programmably determine the frequency of clock pulses provided by said programmable clock pulse divider to said delay counter.

Claim 6

The circuit of claim 3 further comprising a look-up table connected to receive an output of aid acceleration counter to provide an output to said programmable clock pulse divider in accordance with said output of said acceleration counter.

Claim 7

A circuit for operating a polyphase dc motor having a plurality of driving coils that are commutatively energized in a predetermined sequence to produce rotation of a rotor, comprising: a commutation sequence generator for generating commutation sequence signals for controlling which of said plurality of driving coils are energized; circuitry for receiving a back emf of at least one of said driving coils when said at least one of said driving coils is in a floating state; rotor position determining circuitry for determining when the back emf received by said circuitry for receiving the back emf crosses a reference voltage; commutation delay circuitry for determining a delay after an occurrence of the back emf crossing the reference voltage, for initiating a next commutation sequence; a circuit for measuring times between successive occurrences of the back emf crossing the reference voltage, whereby a change in time between successive occurrences of the back emf crossing indicates an acceleration of the rotor; a circuit connected to adjust the delay of said commutation delay circuit in response to the circuit for measuring times between successive occurrences of the back emf crossing the reference voltage indicating an acceleration of the rotor; wherein said circuit connected to adjust the delay of said commutation delay circuit, comprises: an up counter and first and second down counters; a source of clock pulses connected to clock said up and said second down counters; a first programmable clock pulse divider connected to receive and programmably divide said clock pulses to provide clock pulses at a selectively divided frequency to said first down counter; means operative when said reference voltage crossing detector detects a reference voltage crossing to load a count from said up counter into said first and second down counters and then to reset said up counter; an output from said second down counter being connected to programmably determine the frequency of clock pulses provided by said first programmable clock pulse divider; whereby said first counter determines a commutation switching time of said commutation sequence and said second counter determines a acceleration of said rotor.

Claim 8

A circuit for operating a polyphase dc motor having a plurality of driving coils that are commutatively energized in a predetermined sequence to produce rotation of a rotor, comprising: a commutation sequence generator for generating commutation sequence signals for controlling which of said plurality of driving coils are energized; circuitry for receiving a back emf of at least one of said driving coils when said at least one of said driving coils is in a floating state; rotor position determining circuitry for determining when the back emf received by said circuitry for receiving the back emf crosses a reference voltage; commutation delay circuitry for determining a delay after an occurrence of the back emf crossing the reference voltage, for initiating a next commutation sequence; a circuit for measuring times between successive occurrences of the back emf crossing the reference voltage, whereby a change in time between successive occurrences of the back emf crossing indicates an acceleration of the rotor; a circuit connected to adjust the delay of said commutation delay circuit in response to the circuit for measuring times between successive occurrences of the back emf crossing the reference voltage indicating an acceleration of the rotor; wherein said circuit connected to adjust the delay of said commutation delay circuit, comprises: an up counter and first and second down counters; a source of clock pulses connected to clock said up and said second down counters; a first programmable clock pulse divider connected to receive and programmably divide said clock pulses to provide clock pulses at a selectively divided frequency to said first down counter; means operative when said reference voltage crossing detector detects a reference voltage crossing to load a count from said up counter into said first and second down counters and then to reset said up counter; an output from said second down counter being connected to programmably determine the frequency of clock pulses provided by said first programmable clock pulse divider; whereby said first counter determines a commutation switching time of said commutation sequence and said second counter determines a acceleration of said rotor.

Claim 9

The circuit of claim 5 further comprising mask circuitry for inhibiting said circuitry for determining when the back emf received by said circuitry for receiving the back emf crosses a reference voltage for a predetermined time after a change in said commutation sequence.

Claim 10

The circuit of claim 6 further comprising a circuit connected to adjust the length during which said back emf determination is inhibited after a reference voltage crossing, in response to the circuit for measuring times between successive occurrences of the back emf crossing the reference voltage indicating an acceleration of the rotor.

Claim 11

The circuit claim 7 wherein said circuit connected to adjust the length during which said back emf determination is inhibited after a reference voltage crossing, comprises: an up counter and third and second down counters; a source of clock pulses connected to click said up and said second down counters; a second programmable clock pulse divider connected to receive and programmably divide said clock pulses to provide clock pulses at a selectively divided frequency to said third down counter; means operative when said reference voltage crossing detector detects a reference voltage crossing to load a count from said up counter into said third and second down counters and then to reset said up counter; an output from said second down counter being connected to programmably determine the frequency of clock pulses provided by said third programmable clock pulse divider; whereby said second counter determines a acceleration of said rotor, and said third counter determines a mask time duration after a commutation switching in accordance with the acceleration determined by said second counter.

Claim 12

The circuit of claim 8 wherein said reference voltage is zero.

Claim 15

The method of claim 10 further comprising adjusting a noise mask in response to the determined acceleration.

Claim 16

The method of claim 11 wherein said step of adjusting the noise mask comprises adjusting a commutation noise mask.

Claim 17

The method of claim 12 wherein said step of adjusting a commutation noise mask comprises adjusting a duration of a commutation noise mask that prevents detection of a back emf reference voltage crossing for the duration of the commutation noise mask.

Claim 18

The method of claim 11 further comprising performing said steps of adjusting a commutation delay and adjusting a noise mask in response to the determined acceleration comprises continuing the above said adjusting steps from motor startup continuously through operation at normal operating speed.

Claim 19

The method of claim 10 wherein said step of determining an acceleration of a rotor of the motor comprises determining whether said acceleration is a positive or negative acceleration.