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US5164331A
Expired / Lapsed
US
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Method of forming and etching titanium-tungsten interconnects
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1991-10-03
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Granted: 1992-11-17
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Expires: 2011-10-03
Abstract
Abstract A method of forming an interconnect, particularly a local interconnect, for a silicon substrate having integrated circuit devices between dielectric regions. Titanium disilicide is formed on electrode regions of the integrated circuit devices, whereafter titanium-tungsten is deposited across the silicon substrate. A photomask is formed and patterned to cover selected portions of the titanium-tungsten layer. The uncovered portions receive a preliminary etch of chlorine and carbon tetrafluoride to remove oxide. A second etch using trifluoromethane and oxygen removes the uncovered portions, leaving an electrically conductive interconnect extending from an electrode region onto a dielectric region leading to a second electrode region. The photomask is then removed.
Inventors
- 👤 Jung Lin
- 👤 Warren M. Uesato
- 👤 Leuh Fang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:10
CPC Classifications
C; C23; C23F; C23F4/00; H; H10; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; H10W20/40; H10W20/41; H10W20/44; H10W20/4403; H10W20/4437; H10W20/4441
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
51 words
A method of fabricating an interconnect comprising, providing a substrate having integrated circuit devices fabricated thereon, forming a layer of titanium-tungsten atop said substrate, and patterning said titanium-tungsten layer to form an interconnect of an integrated circuit, including dry etching said titanium-tungsten layer using a gas mixture of trifluoromethane and oxygen.
Claim 2
Independent Claim
51 words
A method of fabricating an interconnect comprising, providing a substrate having integrated circuit devices fabricated thereon, forming a layer of titanium-tungsten atop said substrate, and patterning said titanium-tungsten layer to form an interconnect of an integrated circuit, including dry etching said titanium-tungsten layer using a gas mixture of trifluoromethane and oxygen.
Claim 3
Dependent Claim
28 words
The method of claim 1 wherein said step of patterning said titanium-tungsten includes forming a photoresist layer atop said titanium-tungsten layer in a pattern to define said interconnect.
Claim 4
Dependent Claim
22 words
The method of claim 1 further comprising removing oxide from an exposed surface of said titanium-tungsten prior to said step of patterning.
Claim 5
Dependent Claim
28 words
The method of claim 3 wherein said step of removing oxide is a step of directing an ambient of chlorine and carbon tetrafluoride gases to said exposed surfaces.
Claim 6
Dependent Claim
25 words
The method of claim 1 wherein said step of forming said titanium-tungsten layer includes sputter depositing titanium-tungsten onto electrode regions of said integrated circuit devices.
Claim 7
Dependent Claim
23 words
The method of claim 5 further comprising forming a silicide on said active regions prior to said step of forming said titanium-tungsten layer.
Claim 8
Dependent Claim
22 words
The method of claim 4 further comprising removing residue of said chlorine gas from the ambient after said step of removing oxide.
Claim 9
Independent Claim
79 words
A method of forming a chip level interconnect comprising, providing a semiconductor substrate having integrated circuit devices, forming a silicide on electrode regions of said integrated circuit devices, depositing titanium-tungsten on said semiconductor substrate, forming a mask on selected portions of said titanium-tungsten, dry etching portions of said titanium-tungsten uncovered by said mask, including exposing said uncovered portions to CHF 3 and O 2 gases, thereby leaving a chip level interconnect having a desired configuration, and removing said mask.
Claim 10
Independent Claim
79 words
A method of forming a chip level interconnect comprising, providing a semiconductor substrate having integrated circuit devices, forming a silicide on electrode regions of said integrated circuit devices, depositing titanium-tungsten on said semiconductor substrate, forming a mask on selected portions of said titanium-tungsten, dry etching portions of said titanium-tungsten uncovered by said mask, including exposing said uncovered portions to CHF 3 and O 2 gases, thereby leaving a chip level interconnect having a desired configuration, and removing said mask.
Claim 11
Dependent Claim
26 words
The method of claim 8 wherein said step of forming a silicide includes depositing a layer of titanium and reacting said titanium with said electrode regions.
Claim 12
Dependent Claim
57 words
The method of claim 8 wherein said providing a semiconductor substrate includes providing a silicon substrate having dielectric regions and steps from a surface of said silicon substrate to said dielectric regions, said forming said mask including covering titanium-tungsten on a step from said silicon substrate to one of said dielectric regions to form a local interconnect.
Claim 13
Dependent Claim
29 words
The method of claim 8 wherein said dry etching is a plasma etching including introducing said CHF 3 at a rate in the range of 35 to 45 SCCM.
Claim 14
Dependent Claim
25 words
The method of claim 11 wherein said plasma etching includes introducing said O 2 at a rate in the range of 40 to 60 SCCM.
Claim 15
Dependent Claim
36 words
The method of claim 8 further comprising removing oxide from said uncovered portion of said titanium-tungsten prior to said dry etching, said removing oxide including introducing Cl 2 and CF 4 gases to said silicon substrate.
Claim 16
Dependent Claim
19 words
The method of claim 8 further comprising introducing nitrogen into said titanium-tungsten after said step of removing said mask.
Claim 17
Independent Claim
100 words
A method of forming a local interconnect comprising, fabricating transistors between dielectric regions of a silicon substrate, thereby providing steps from electrode regions of said transistors to said dielectric regions, forming TiSi 2 on said electrode regions, sputter depositing titanium-tungsten on said silicon substrate, depositing a photomask on said titanium-tungsten, patterning said photomask to expose portions of said titanium-tungsten, plasma etching said exposed portions of said titanium-tungsten using CHF 3 and O 2 , thereby leaving a local interconnect atop one of said steps and extending from a first electrode region to a second electrode region, and removing said photomask.
Claim 18
Independent Claim
100 words
A method of forming a local interconnect comprising, fabricating transistors between dielectric regions of a silicon substrate, thereby providing steps from electrode regions of said transistors to said dielectric regions, forming TiSi 2 on said electrode regions, sputter depositing titanium-tungsten on said silicon substrate, depositing a photomask on said titanium-tungsten, patterning said photomask to expose portions of said titanium-tungsten, plasma etching said exposed portions of said titanium-tungsten using CHF 3 and O 2 , thereby leaving a local interconnect atop one of said steps and extending from a first electrode region to a second electrode region, and removing said photomask.
Claim 19
Dependent Claim
15 words
The method of claim 15 wherein said etching includes an overetching of at least 100%.
Claim 20
Dependent Claim
20 words
The method of claim 15 wherein said step of sputter depositing is a depositing of a layer 100 nm thick.
Claim 21
Dependent Claim
23 words
The method of claim 15 further comprising removing oxide from said exposed portions of said titanium-tungsten using Cl 2 and CF 4 gases.
Claim 22
Dependent Claim
40 words
The method of claim 15 wherein said plasma etching includes introducing said CHF 3 at a rate in the range of 35 to 45 SCCM and introducing O 2 at a rate in the range of 40 to 60 SCCM.
Claim 23
Dependent Claim
21 words
The method of claim 19 wherein said plasma etching is at a pressure in the range of 30 to 40 mtorr.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-17 | 1996-05-18 | 1996-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-17 | 2000-05-18 | 2000-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-17 | 2004-05-18 | 2004-11-17 | $7700.00 | Window Closed / Lapsed |