Digital modulation circuit

Claim 2

A modulator circuit for generating a modulated, DQPSK signal of a desired bandwidth responsive to application of an input signal representative of differential signal phase changes, said modulator circuit comprising: an encoder for converting the input signal representative of the differential signal phase changes into an encoded signal representative of a signal formed of an I-component portion and a Q-component portion; means for storing sequences of the encoded signal representative of the signal formed of the I-component portion and the Q-component portion generated by said encoder; a memory element for storing values corresponding to possible values of an I-component portion and a Q-component portion, respectively, of an input signal multiplied by values of an impulse response of a filter, each value stored therein forming a weighted value thereby; means for summing weighted values stored in the memory element corresponding to sequences of the encoded signal stored by said means for storing and for forming summed, weighted values indicative of summations thereof; and means for generating signals indicative of the summed, weighted values formed by the means for summing, said signals formed thereby forming the modulated, DQPSK signal of the desired bandwidth.

Claim 3

The modulator circuit of claim 1 wherein the encoded signal formed by said encoder comprises a first, three-bit, encoded signal wherein a first bit of the first, three-bit, encoded signal indicates times when the I-component portion of the encoded signal is of a zero value, a second bit of the three-bit, encoded signal indicates polarity of the I-component portion of the encoded signal, and a third bit of the first, three-bit, encoded signal indicates magnitudes of the I-component portion of the encoded signal.

Claim 4

The modulator circuit of claim 1 wherein the encoded signal formed by said encoder comprises a second, three-bit, encoded signal wherein a first bit of the second, three bit, encoded signal indicates times when the Q-component portion of the encoded signal is of a zero value, a second bit of the second, three-bit, encoded signal indicates polarity of the Q-component portion of the encoded signal, and a third bit of the second, three-bit, encoded signal indicates magnitudes of the Q-component portion of the encoded signal.

Claim 5

The modulator circuit of claim 1 wherein said encoder generates a five-bit, encoded signal wherein a first bit of said five-bit, encoded signal indicates times when the I-component portion of the encoded signal is of a zero value; a second bit of the five-bit encoded signal indicates polarity of the I-component portion of the encoded signal; a third bit of the five-bit, encoded signal indicates times when the Q-component portion of the encoded signal is of a zero value; a fourth bit of the five-bit, encoded signal indicates polarity of the Q-component portion of the encoded signal; and a fifth bit of the five-bit, encoded signal indicates magnitudes of the I-component portion and the Q-component portion of the encoded signal.

Claim 6

The modulator circuit of claim 4 wherein said means for storing comprises at least on shift register for storing component values of sequences of the I-component and Q-component portions, respectively, of the encoded signal.

Claim 7

The modulator circuit of claim 5 wherein said at least on shift register comprises a plurality of shift registers, each associated with a bit of the five-bit, encoded signal for storing sequences of bits of respective ones of bits of the five-bit, encoded signal therein.

Claim 8

The modulator circuit of claim 1 wherein said encoder is comprised of a first encoder portion and a second encoder portion wherein said first encoder portion generates a first, two-bit encoded signal, and said second encoder portion generates two sets of two-bit encoded signals.

Claim 9

The modulator circuit of claim 7 wherein said means for storing comprises first and second shift registers each associated with a bit of the first, two-bit encoded signal for storing sequences of bits of respective ones of bits of the first, two-bit, encoded signal therein.

Claim 10

The modulator circuit of claim 7 further comprising means for generating a clock signal wherein a clock signal generated therefrom together with the sets of two-bit encoded signals form the encoded signal generated by the encoder.

Claim 11

The modulator circuit of claim 1 wherein said means for summing comprises an in-phase accumulator for summing sequences of the I-component portions of the encoded signal.

Claim 12

The modulator circuit of claim 1 wherein said means for summing comprises a quadrature-phase accumulator for summing sequences of the O-component portions of the input signal.

Claim 13

The modulator circuit of claim 1 wherein said impulse response of the filter utilized to form the weighted value forms a sinc function.

Claim 14

The modulator circuit of claim 1 wherein said filter of which the impulse response thereof is utilized to form the weighted value comprises a square-root, raised cosine, low pass filter.

Claim 15

The modulator circuit of claim 1 wherein said possible values of the I-component portion and the Q-component portion, respectively, of the input signal comprises normalized values of "1" and "0.707".

Claim 16

The modulator circuit of claim 1 wherein said values of the impulse response function comprise values corresponding to sixteen points taken across a plot of the impulse response of the filter.

Claim 17

The modulator circuit of claim 1 wherein said means for generating comprises means forming a digital to analog converter for receiving the summed, weighted values formed by said means for summing and for generating analog signals indicative thereof.

Claim 18

The modulator circuit of claim 1 further comprising means for up-converting the signals indicative of the summed, weighted values generated by said means for generating to a transmission frequency to form a radio frequency, DQPSK-modulated signal thereby.

Claim 19

The modulator circuit of claim 17 wherein said means for up-converting comprises a quadrature modulator.

Claim 20

A circuit for generating a filtered, DQPSK signal responsive to application thereto of an input signal representative of differential signal phase changes having an I-component portion and a Q-component portion, said circuit comprising: at least one shift register for storing component values indicative of magnitudes of component portions of sequences of the input signal; means for summing weighted values of the stored component values indicative of the magnitudes of component portions of sequences of the input signal and for forming summed, weighted values therefrom; and means for generating signals indicative of the summed, weighted values generated by the means for summing.

Claim 21

A circuit for generating a filtered, DQPSK signal responsive to application thereto of an input signal representative of differential signal phase changes having an I-component portion and a Q-component portion, said circuit comprising: at least one shift register for storing component values indicative of magnitudes of component portions of sequences of the input signal; means for summing weighted values of the stored component values indicative of the magnitudes of component portions of sequences of the input signal and for forming summed, weighted values therefrom; and means for generating signals indicative of the summed, weighted values generated by the means for summing.

Claim 22

The circuit of claim 19 wherein a shift register of said at least one shift register stores component values to indicate times when the I-component portion of the input signal is of a zero value.

Claim 23

The circuit of claim 19 wherein a shift register of said at least one shift register stores component values indicative of an I-component portion polarity of the I-component portion of the input signal.

Claim 24

The circuit of claim 19 wherein a shift register of said at least one shift register stores component values to indicate times when the Q-component portion of the input signal is of a zero value.

Claim 25

The circuit of claim 19 wherein a shift register of said at least one shift register stores component values indicative of a Q-component portion polarity of the Q-component portion of the input signal.

Claim 26

The circuit of claim 19 wherein said means for summing comprises an in-phase accumulator for summing sequences of the I-component portion values of the input signal.

Claim 27

The circuit of claim 19 wherein said means for summing comprises a quadrature-phase accumulator for summing sequences of the Q-component portion values of the input signal.

Claim 28

The circuit of claim 19 further comprising means for forming the weighted values summed by said means for summing.

Claim 29

The circuit of claim 26 wherein said means for forming the weighted values comprises a memory element for storing values corresponding to possible values of the I-component portion and the Q-component portion, respectively, of the input signal multiplied by values of a filter impulse response function.

Claim 30

The circuit of claim 27 wherein said filter impulse response function forms a sinc function.

Claim 31

The circuit of claim 27 wherein possible values of the I-component portion and the Q-component portion, respectively, of the input signal comprises normalized values of "1" and "0.707".

Claim 32

The circuit of claim 27 wherein said values of the filter impulse response function comprises values corresponding to sixteen points taken across the filter impulse response function.

Claim 33

The circuit of claim 19 wherein said means for generating comprises means forming a digital to analog converter for receiving the summed, weighted values formed by said means for summing and for generating analog signals indicative thereof.

Claim 34

A transmitter circuit for generating a radio frequency, DQPSK-modulated signal responsive to application of an input signal representative of differential signal phase changes, said transmitter circuit comprising: an encoder for generating an encoded signal representative of an I-component portion and a Q-component portion of the input signal, said encoded signal generated thereby comprised of at least five bits wherein a first bit of the at least five bits indicates times when the I-component portion of the input signal is of a zero value; a second bit of the at least five bits indicates polarity of the I-component portion of the input signal; a third bit of the at least five bits indicates times when the Q-component portion of the input signal is of a zero value; a fourth bit of the at least five bits indicates polarity of the Q-component portion of the input signal; and a fifth bit of the at least five bits indicates magnitudes of the I-component portion and the Q-component portion of the input signal; a plurality of shift registers, each associated with a bit of the at least five bits of the encoded signal for storing sequences of bits of respective ones of bits of the at least five bits therein; a memory element for storing values corresponding to possible values of the I-component portion and the Q-component portion, respectively, of the input signal multiplied by values of a filter impulse response function; an in-phase accumulator coupled to receive sequences of portions of said encoded signal generated by the encoder and sequences of values stored in the memory element, each of the sequences received by the in-phase accumulator, respectively, corresponding to values of the I-component portion of the encoded signal generated by the encoder, said in-phase accumulator for summing sequences of the I-component portion of the encoded signal and for forming in-phase, summed signals indicative thereof; a quadrature phase accumulator coupled to receive sequences of portions of said encoded signal generated by the encoder and sequences of values stored in the memory element, each of said sequences received by the quadrature-phase accumulator, respectively, corresponding to values of the Q-component portion of the encoded signal generated by the encoder, said quadrature-phase accumulator for summing sequences of the Q-component portion of the encoded signal and for forming quadrature-phase, summed signals indicative thereof; at least one digital-to-analog converter for receiving the in-phase, summed signals and the quadrature-phase, summed signals formed by the in-phase accumulator and the quadrature-phase accumulator, respectively, and for generating analog, in-phase, summed signals and analog, quadrature-phase, summed signals therefrom; and a quadrature modulator for up-converting said analog, in phase, summed signals and said analog, quadrature-phase summed signals generated by the at least one digital to analog converter to a transmission frequency to form a radio frequency DQPSK-modulated signal thereby.

Claim 35

A transmitter circuit for generating a radio frequency, DQPSK-modulated signal responsive to application of an input signal representative of differential signal phase changes, said transmitter circuit comprising: an encoder for generating an encoded signal representative of an I-component portion and a Q-component portion of the input signal, said encoded signal generated thereby comprised of at least five bits wherein a first bit of the at least five bits indicates times when the I-component portion of the input signal is of a zero value; a second bit of the at least five bits indicates polarity of the I-component portion of the input signal; a third bit of the at least five bits indicates times when the Q-component portion of the input signal is of a zero value; a fourth bit of the at least five bits indicates polarity of the Q-component portion of the input signal; and a fifth bit of the at least five bits indicates magnitudes of the I-component portion and the Q-component portion of the input signal; a plurality of shift registers, each associated with a bit of the at least five bits of the encoded signal for storing sequences of bits of respective ones of bits of the at least five bits therein; a memory element for storing values corresponding to possible values of the I-component portion and the Q-component portion, respectively, of the input signal multiplied by values of a filter impulse response function; an in-phase accumulator coupled to receive sequences of portions of said encoded signal generated by the encoder and sequences of values stored in the memory element, each of the sequences received by the in-phase accumulator, respectively, corresponding to values of the I-component portion of the encoded signal generated by the encoder, said in-phase accumulator for summing sequences of the I-component portion of the encoded signal and for forming in-phase, summed signals indicative thereof; a quadrature phase accumulator coupled to receive sequences of portions of said encoded signal generated by the encoder and sequences of values stored in the memory element, each of said sequences received by the quadrature-phase accumulator, respectively, corresponding to values of the Q-component portion of the encoded signal generated by the encoder, said quadrature-phase accumulator for summing sequences of the Q-component portion of the encoded signal and for forming quadrature-phase, summed signals indicative thereof; at least one digital-to-analog converter for receiving the in-phase, summed signals and the quadrature-phase, summed signals formed by the in-phase accumulator and the quadrature-phase accumulator, respectively, and for generating analog, in-phase, summed signals and analog, quadrature-phase, summed signals therefrom; and a quadrature modulator for up-converting said analog, in phase, summed signals and said analog, quadrature-phase summed signals generated by the at least one digital to analog converter to a transmission frequency to form a radio frequency DQPSK-modulated signal thereby.

Claim 38

A modulator circuit for generating a modulated, DQPSK signal of a desired bandwidth responsive to application of an input signal representative of differential signal phase changes, said modulator circuit comprising: an encoder for converting the input signal representative of the differential signal phase changes into a five-bit, encoded signal representative of a signal formed of an I-component portion and a Q-component portion wherein a first bit of said five-bit, encoded signal indicates times when the I-component portion of the encoded signal is of a zero value; a second bit of the five-bit encoded signal indicates polarity of the I-component portion of the encoded signal; a third bit of the five-bit, encoded signal indicates times when the Q-component portion of the encoded signal is of a zero value; a fourth bit of the five-bit, encoded signal indicates polarity of the Q-component portion of the encoded signal; and a fifth bit of the five-bit, encoded signal indicates magnitudes of the I-component portion and the Q-component portion of the encoded signal. means for storing sequences of the five-bit, encoded signal representative of the signal formed of the I-component portion and the Q-component portion generated by said encoder; a memory element for storing values corresponding to possible values of an I-component portion and a Q-component portion, respectively, of an input signal multiplied by values of an impulse response of a filter, each value stored therein forming a weighted value thereby; means for summing weighted values stored in the memory element corresponding to sequences of the encoded signal stored by said means for storing and for forming summed, weighted values indicative of summations thereof; and means for generating signals indicative of the summed, weighted values formed by the means for summing, said signals formed thereby forming the modulated, DQPSK signal of the desired bandwidth.

Claim 39

A modulator circuit for generating a modulated, DQPSK signal of a desired bandwidth responsive to application of an input signal representative of differential signal phase changes, said modulator circuit comprising: an encoder for converting the input signal representative of the differential signal phase changes into a five-bit, encoded signal representative of a signal formed of an I-component portion and a Q-component portion wherein a first bit of said five-bit, encoded signal indicates times when the I-component portion of the encoded signal is of a zero value; a second bit of the five-bit encoded signal indicates polarity of the I-component portion of the encoded signal; a third bit of the five-bit, encoded signal indicates times when the Q-component portion of the encoded signal is of a zero value; a fourth bit of the five-bit, encoded signal indicates polarity of the Q-component portion of the encoded signal; and a fifth bit of the five-bit, encoded signal indicates magnitudes of the I-component portion and the Q-component portion of the encoded signal. means for storing sequences of the five-bit, encoded signal representative of the signal formed of the I-component portion and the Q-component portion generated by said encoder; a memory element for storing values corresponding to possible values of an I-component portion and a Q-component portion, respectively, of an input signal multiplied by values of an impulse response of a filter, each value stored therein forming a weighted value thereby; means for summing weighted values stored in the memory element corresponding to sequences of the encoded signal stored by said means for storing and for forming summed, weighted values indicative of summations thereof; and means for generating signals indicative of the summed, weighted values formed by the means for summing, said signals formed thereby forming the modulated, DQPSK signal of the desired bandwidth.

Claim 40

A circuit for generating a filtered, DQPSK signal responsive to application thereto of an input signal representative of differential signal phase changes having an I-component portion and a Q-component portion, said filter comprising: means for storing sequences of the input signal; a memory element for storing values corresponding to possible values of an I-component portion and a Q-component portion, respectively, of an input signal multiplied by values of an impulse response of a filter, whereby each product derived thereby forms a weighted value; means for summing weighted values stored in the memory element corresponding to sequences of the input signal stored by said means for storing and for forming summed, weighted values indicative of summations thereof; and means for generating signals indicative of the summed, weighted values generated by the means for summing.

Claim 41

A circuit for generating a filtered, DQPSK signal responsive to application thereto of an input signal representative of differential signal phase changes having an I-component portion and a Q-component portion, said filter comprising: means for storing sequences of the input signal; a memory element for storing values corresponding to possible values of an I-component portion and a Q-component portion, respectively, of an input signal multiplied by values of an impulse response of a filter, whereby each product derived thereby forms a weighted value; means for summing weighted values stored in the memory element corresponding to sequences of the input signal stored by said means for storing and for forming summed, weighted values indicative of summations thereof; and means for generating signals indicative of the summed, weighted values generated by the means for summing.