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US4613976A Expired / Lapsed US ⏱️ 0.0 years remaining

Constant envelope offset QPSK modulator

Assignee: British Columbia Telephone Co
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Filing: 1984-05-02
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Granted: 1986-09-23
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Expires: 2004-05-02
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Abstract

Abstract The modulator comprises a serial to parallel converter which separates alternate bits of a serial-binary data stream into I and Q bit streams that are stored in associated shift registers, a pair of ROMs that drive associated D/A converters, and a quadrature-phase modulator. Each bit of the I and Q bit streams has a duration of 2T, where T is the bit interval or period of a data bit. Each of the ROMs comprises blocks of memory that contain a plurality of digital words. The present and immediate past I and Q bits in the shift registers, and a baud clock signal of one-half the data signal rate, are applied to address inputs of the ROMs for selecting associated memory blocks in the 2 ROMs. A counter then clocks the ROMs for sequentially outputting the contents of the addressed memory blocks to the converters which produce analog voltages that phase modulate a carrier signal for moving a resultant signal vector with a constant envelope during each bit interval. The contents of the ROMs are selected to provide a substantially constant amplitude vector whose rate of change w of phase satisfies the criteria: ______________________________________ I(t) = I(t - 2T) Q(t) = Q(t - 2T) |w| ______________________________________ yes yes O yes no W no yes W no no 2W ______________________________________ where W and 2W are constant phase velocities that rotate the signal vector a total of 45° and 90°, respectively, in a bit or symbol interval.

Inventors

  • 👤 Ake Sewerinson
  • 👤 Andrew V. Hellquist

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 06:48
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/20; H04L27/2032; H04L27/2053; H04L27/206; H04L27/2067; H04L27/2071

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 390 words
Apparatus for transforming a serial input data signal into a substantially constant envelope offset phase shift keying modulated signal vector, comprising: first means for generating a baud clock having a repetition rate that is one-half that of the data signal; second means for directing alternate data bits in the input data signal into in-phase and quadrature-phase I and Q pulse trains, with the present data bit that is entered into a pulse train being held constant for the time interval 2T of the present and next data bits which have a symbol interval T; storage means for storing a present and past bit for each of the I and Q pulse trains; a quadrature-phase modulator for combining quadrature-phase sinusoidal carrier signals with associated ones of first and second input signals for generating the phase modulated signal vector; and third means responsive to the baud clock and the present and a prior bit from each of the I and Q pulse trains during each symbol interval for generating associated series of analog voltages which are said first and second input signals and which cause the rate of change w of the phase of the signal vector during each symbol interval to satisfy the criteria: ______________________________________ I(t) = I(t - nT) Q(t) = Q(t - nT) |w| ______________________________________ yes yes O yes no W no yes W no no 2W ______________________________________ where W and 2W are constant phase velocities that rotate the signal vector a total of 45° and 90°, respectively, in a symbol interval; n is an integer; t is time; I(t) and Q(t) are the present bits; and I(t-nT) and Q(t-nT) are prior bits in the I and Q pulse trains; wherein n=2 and I(t-2T) and Q(t-2T) are the bits immediately preceeding the present bits in the I and Q pulse trains; and wherein said series of voltages from said third means cause rotation of the signal vector either clockwise or counterclockwise when the baud clock is one of a binary 1 and 0 and the bit I(t-2T) is not equal to and is equal to the bit Q(t), respectively; and rotation of the signal vector either counterclockwise or clockwise when the baud clock is the other of a binary 1 and 0 and the the bit I(t) is not equal to and is equal to the bit Q(t-2T), respectively.
Claim 2
Dependent Claim 390 words
Apparatus for transforming a serial input data signal into a substantially constant envelope offset phase shift keying modulated signal vector, comprising: first means for generating a baud clock having a repetition rate that is one-half that of the data signal; second means for directing alternate data bits in the input data signal into in-phase and quadrature-phase I and Q pulse trains, with the present data bit that is entered into a pulse train being held constant for the time interval 2T of the present and next data bits which have a symbol interval T; storage means for storing a present and past bit for each of the I and Q pulse trains; a quadrature-phase modulator for combining quadrature-phase sinusoidal carrier signals with associated ones of first and second input signals for generating the phase modulated signal vector; and third means responsive to the baud clock and the present and a prior bit from each of the I and Q pulse trains during each symbol interval for generating associated series of analog voltages which are said first and second input signals and which cause the rate of change w of the phase of the signal vector during each symbol interval to satisfy the criteria: ______________________________________ I(t) = I(t - nT) Q(t) = Q(t - nT) |w| ______________________________________ yes yes O yes no W no yes W no no 2W ______________________________________ where W and 2W are constant phase velocities that rotate the signal vector a total of 45° and 90°, respectively, in a symbol interval; n is an integer; t is time; I(t) and Q(t) are the present bits; and I(t-nT) and Q(t-nT) are prior bits in the I and Q pulse trains; wherein n=2 and I(t-2T) and Q(t-2T) are the bits immediately preceeding the present bits in the I and Q pulse trains; and wherein said series of voltages from said third means cause rotation of the signal vector either clockwise or counterclockwise when the baud clock is one of a binary 1 and 0 and the bit I(t-2T) is not equal to and is equal to the bit Q(t), respectively; and rotation of the signal vector either counterclockwise or clockwise when the baud clock is the other of a binary 1 and 0 and the the bit I(t) is not equal to and is equal to the bit Q(t-2T), respectively.
Claim 3
Dependent Claim 142 words
Apparatus according to claim 1 wherein said third means comprises: a pair of digital to analog converters having output signals which are said input signals to said modulator; timing means providing a plurality of stepping pulses during each symbol interval; and first and second read only memories comprising blocks of memory that contain a plurality of digital words, each of said memories being responsive to the baud clock and binary indications of the present and past I and Q bits from said storage means for selecting a prescribed block of memory and responsive to the stepping pulses for outputting a series of digital words that are applied to an associated converter for producing a series of analog voltages, said voltages from said converters causing the direction and rate of change of the phase of the signal vector to satisfy the prescribed criteria.
Claim 4
Independent Claim 287 words
A method of generating a constant envelope offset phase shift keying modulated signal vector from a digital input data signal in which alternate bits are directed into in-phase I and quadrature-phase Q channels, with the current bit that is entered into each channel being held constant for a time interval 2T of the current and next data bits, and wherein the phase of the signal vector varies by prescribed amounts and in prescribed directions during a symbol interval T of each data bit, comprising the steps of: causing the rate of change w of phase to be determined as follows: ______________________________________ I(t) = I(t - 2T) Q(t) = Q(t - 2T) |w| ______________________________________ yes yes O yes no W no yes W no no 2W ______________________________________ where I(t) and Q(t) represent the current data bits in the in-phase and quarature-phase channels, respectively; I(t-2T) and Q(t-2T) represent the immediate past data bits in the in-pase and quadrature-phase channels, respectively; I(t)=I(t-2T) and Q(t)=Q(t-2T) are identities; w is the phase velocity or rate of change of phase; and W and 2W are constant phase velocities that will rotate the signal vector a total of 45° and 90°, respectively, in one bit time T; generating a baud clock signal having a repetition rate which is one-half that of the input data signal; and performing one of the steps of: rotating the signal vector either counterclockwise or clockwise when the baud clock is one of a binary 1 and 0 and the identity I(t-2T)=Q(t) is satisfied and not satisfied, respectively; and rotating the signal vector either clockwise or counterclockwise when the baud clock is the other of a binary 1 and 0 and the identity I(t)=Q(t-2T) is satisfied and not satisfied, respectively.
Claim 5
Independent Claim 287 words
A method of generating a constant envelope offset phase shift keying modulated signal vector from a digital input data signal in which alternate bits are directed into in-phase I and quadrature-phase Q channels, with the current bit that is entered into each channel being held constant for a time interval 2T of the current and next data bits, and wherein the phase of the signal vector varies by prescribed amounts and in prescribed directions during a symbol interval T of each data bit, comprising the steps of: causing the rate of change w of phase to be determined as follows: ______________________________________ I(t) = I(t - 2T) Q(t) = Q(t - 2T) |w| ______________________________________ yes yes O yes no W no yes W no no 2W ______________________________________ where I(t) and Q(t) represent the current data bits in the in-phase and quarature-phase channels, respectively; I(t-2T) and Q(t-2T) represent the immediate past data bits in the in-pase and quadrature-phase channels, respectively; I(t)=I(t-2T) and Q(t)=Q(t-2T) are identities; w is the phase velocity or rate of change of phase; and W and 2W are constant phase velocities that will rotate the signal vector a total of 45° and 90°, respectively, in one bit time T; generating a baud clock signal having a repetition rate which is one-half that of the input data signal; and performing one of the steps of: rotating the signal vector either counterclockwise or clockwise when the baud clock is one of a binary 1 and 0 and the identity I(t-2T)=Q(t) is satisfied and not satisfied, respectively; and rotating the signal vector either clockwise or counterclockwise when the baud clock is the other of a binary 1 and 0 and the identity I(t)=Q(t-2T) is satisfied and not satisfied, respectively.
Claim 6
Dependent Claim 43 words
The method accordint claim 3 wherein each bit time T is divided into a plurality N of steps and the incremental change of phase for each step is 90°/N when neither of the identities in claim 1 is satisfied, i.e., row 4 there.
Claim 7
Dependent Claim 47 words
The method according to claim 3 wherein each bit time T is divided into a plurality N of steps and the incremental change of phase for each step is 45°/N when only one of the identities in claim 1 is satisfied, i.e., rows 2 and/or 3 there.
Claim 8
Dependent Claim 15 words
The method according to claim 4 wherein the phase of the modulated signal is continuous.
Claim 9
Dependent Claim 292 words
Apparatus for transforming a serial input data signal into a substantially constant envelope offset phase shift keying modulated signal vector, comprising: first means for generating a baud clock having a repetition rate that is one-half that of the data signal; second means for directing alternate data bits in the input data signal into in-phase and quadrature-phase I and Q pulse trains, with the present data bit that is entered into a pulse train being held constant for the time interval 2T of the present and next data bits which have a symbol interval T; storage means for storing a present and past bit for each of the I and Q pulse trains; a quadrature-phase modulator for combining quadrature-phase sinusoidal carrier signals with associated ones of first and second input signals for generating the phase modulated signal vector; and third means comprising a memory means that is reponsive to the baud clock and to address defined by the stored present and a prior bit from each of the I and Q pulse trains during each symbol interval for generating associated series of analog voltages which are said first and second input signals and which cause the rate of change w of the phase of the signal vector during each symbol interval to satisfy the criteria: ______________________________________ I(t) = I(t - nT) Q(t) = Q(t - nT) |w| ______________________________________ yes yes O yes no W no yes W no no 2W ______________________________________ where W and 2W are constant phase velocities that rotate the signal vector a total of 45° and 90°, respectively, in a symbol interval; n is an integer; t is time; I(t) and Q(t) are the present bits; and I(t-nT) and Q(t-nT) are prior bits in the I and Q pulse trains.
Claim 10
Dependent Claim 292 words
Apparatus for transforming a serial input data signal into a substantially constant envelope offset phase shift keying modulated signal vector, comprising: first means for generating a baud clock having a repetition rate that is one-half that of the data signal; second means for directing alternate data bits in the input data signal into in-phase and quadrature-phase I and Q pulse trains, with the present data bit that is entered into a pulse train being held constant for the time interval 2T of the present and next data bits which have a symbol interval T; storage means for storing a present and past bit for each of the I and Q pulse trains; a quadrature-phase modulator for combining quadrature-phase sinusoidal carrier signals with associated ones of first and second input signals for generating the phase modulated signal vector; and third means comprising a memory means that is reponsive to the baud clock and to address defined by the stored present and a prior bit from each of the I and Q pulse trains during each symbol interval for generating associated series of analog voltages which are said first and second input signals and which cause the rate of change w of the phase of the signal vector during each symbol interval to satisfy the criteria: ______________________________________ I(t) = I(t - nT) Q(t) = Q(t - nT) |w| ______________________________________ yes yes O yes no W no yes W no no 2W ______________________________________ where W and 2W are constant phase velocities that rotate the signal vector a total of 45° and 90°, respectively, in a symbol interval; n is an integer; t is time; I(t) and Q(t) are the present bits; and I(t-nT) and Q(t-nT) are prior bits in the I and Q pulse trains.
Claim 11
Dependent Claim 26 words
Apparatus according to claim 7 wherein n=2 and I(t-2T) and Q(t-2T) are the bits immediately preceeding the present bits in the I and Q pulse trains.
Claim 12
Dependent Claim 215 words
In a method of generating a constant envelope offset phase shift keyed modulated signal vector from a digital input data signal in which alternate bits are directed into in-phase I and quadrature-phase Q channels, with the current bit that is entered into each channel being held constant for a time interval 2T of the current and next data bits, and wherein the phase of the signal vector is varied by prescribed amounts and in prescribed directions during a symbol interval T of each data bit in response to signals produced in the I and Q channels, the improvement comprising the step of causing the rate of change w of phase to be determined as follows: ______________________________________ I(t) = I(t - 2T) Q(t) = Q(t - 2T) |w| ______________________________________ yes yes O yes no W no yes W no no 2W ______________________________________ where I(t) and Q(t) represent the current data bits in the in-phase and quadrature-phase channels, respectively; I(t-2T) and Q(t-2T) represent the immediate past data bits in the in-phase and quadrature-phase channels, respectively; I(t)=I(t-2T) and Q(t)=Q(t-2T) are identities; w is the phase velocity or rate of change of phase; and W and 2W are constant phase velocities that will rotate the signal vector a total of 45° and 90°, respectively, in one bit time T.
Claim 13
Dependent Claim 215 words
In a method of generating a constant envelope offset phase shift keyed modulated signal vector from a digital input data signal in which alternate bits are directed into in-phase I and quadrature-phase Q channels, with the current bit that is entered into each channel being held constant for a time interval 2T of the current and next data bits, and wherein the phase of the signal vector is varied by prescribed amounts and in prescribed directions during a symbol interval T of each data bit in response to signals produced in the I and Q channels, the improvement comprising the step of causing the rate of change w of phase to be determined as follows: ______________________________________ I(t) = I(t - 2T) Q(t) = Q(t - 2T) |w| ______________________________________ yes yes O yes no W no yes W no no 2W ______________________________________ where I(t) and Q(t) represent the current data bits in the in-phase and quadrature-phase channels, respectively; I(t-2T) and Q(t-2T) represent the immediate past data bits in the in-phase and quadrature-phase channels, respectively; I(t)=I(t-2T) and Q(t)=Q(t-2T) are identities; w is the phase velocity or rate of change of phase; and W and 2W are constant phase velocities that will rotate the signal vector a total of 45° and 90°, respectively, in one bit time T.

References Cited (Backward Citations)

US3643023A Cited
US3916101A Cited
US4008373A Cited
US4229821A Cited
US4168397A Cited
US4417219A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-09-22 1990-03-24 1990-09-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-09-22 1994-03-24 1994-09-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-09-22 1998-03-24 1998-09-23 $7700.00 Window Closed / Lapsed

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