Method and apparatus for preventing recursion jeopardy

Claim 2

A digital data processor comprising: a bus; a first register set coupled to the bus; a second register set coupled to the bus; a first status bit coupled to the bus; a second status bit coupled to the bus; central processing unit means coupled to the bus for utilizing said first and second register sets one at a time; first interrupt receiving means coupled to the central processing unit and to a first interrupt request signal conductor for receiving interrupt requests of a first type; second interrupt receiving means coupled to the central processing unit and to a second interrupt request signal conductor for receiving interrupt requests of a second type; state determining means coupled to the first and second status bits and the first and second interrupt receiving means for determining, in response to receipt of an interrupt request by either the first or second interrupt receiving means, whether the interrupt request is of the first type or the second type, whether the first status bit is in a first state or a second state and whether the second status bit is in the first state or the second state; and register set selecting means coupled to the state determining means and to the central processing unit means for selecting, in response to receipt of an interrupt request by either the first or second interrupt receiving means, one of the first and second register sets for utilization by the central processing unit means, the selection by the register set selecting means is dependent upon determinations of the state determining means.

Claim 3

A digital data processor according to claim 1 further comprising: next state determining means coupled to the first and second status bits and the first and second interrupt receiving means for determining, in response to receipt of an interrupt request by either the first or second interrupt receiving means, new values of the first and second status bits.

Claim 4

A digital data processor according to claim 2 further comprising: a first control bit coupled to the bus and to the register set selecting means, a state of the first control bit indicates which of the first and second register sets is presently being utilized by the central processing unit means and the central processing unit means is capable of determining the state of the first control bit independent of the register set selecting means.

Claim 5

A digital data processor according to claim 2 wherein the states of the first and second status bits, taken together, indicate one of: that no interrupt request of the second type has been received that has not been completed; that only one interrupt request of the second type has been received and that a most recent interrupt request received was of the second type; that more than one interrupt request of the second type has been received and that a most recent interrupt request received was of the second type; and that at least one of the second type of interrupt request has been received and that a most recent interrupt request received was of the first type.

Claim 6

A digital data processor according to claim 2 further comprising: a third status bit coupled to the bus; and wherein the first, second and third status bits, taken together, indicate one of: that no interrupt request of the second type has been received that has not been completed; that only one interrupt request of the second type has been received and that a most recent interrupt request received was of the second type; that more than one interrupt request of the second type has been received and that a most recent interrupt request received was of the second type; and that at least one of the second type of interrupt request has been received and that a most recent interrupt request received was of the first type.

Claim 7

A digital data processor according to claim 5 wherein the first status bit, if in the first state, indicates: that no interrupt request of the second type has been received that has not been completed.

Claim 8

A digital data processor according to claim 5 wherein the second status bit, if in the second state, indicates: that only one interrupt request of the second type has been received and that a most recent interrupt request received was of the second type.

Claim 9

A digital data processor according to claim 5 wherein the third status bit, if in the second state, indicates: that a most recent interrupt request received and not completed was of the second type.

Claim 10

A digital data processor comprising: a bus; a first register set coupled to the bus, the first register set further comprising: a first register subset; and a second register subset; a second register set coupled to the bus, the second register set further comprising: a third register subset; and a fourth register subset; a first status bit coupled to the bus; a second status bit coupled to the bus; central processing unit means coupled to the bus for utilizing said first and second register sets one at a time; first interrupt receiving means coupled to the central processing unit and to a first interrupt request signal conductor for receiving interrupt requests of a first type; second interrupt receiving means coupled to the central processing unit and to a second interrupt request signal conductor for receiving interrupt requests of a second type; state determining means coupled to the first and second status bits and the first and second interrupt receiving means for determining, in response to receipt of an interrupt request by either the first or second interrupt receiving means, whether the interrupt request is of the first type or the second type, whether the first status bit is in a first state or a second state and whether the second status bit is in the first state or the second state; and register set selecting means coupled to the state determining means and to the central processing unit means for selecting, in response to receipt of an interrupt request by either the first or second interrupt receiving means, one of the first and third register subsets and one of the second and fourth register subsets for utilization by the central processing unit means, the selection by the register set selecting means is dependent upon determinations of the state determining means.

Claim 11

A digital data processor comprising: a bus; a first register set coupled to the bus, the first register set further comprising: a first register subset; and a second register subset; a second register set coupled to the bus, the second register set further comprising: a third register subset; and a fourth register subset; a first status bit coupled to the bus; a second status bit coupled to the bus; central processing unit means coupled to the bus for utilizing said first and second register sets one at a time; first interrupt receiving means coupled to the central processing unit and to a first interrupt request signal conductor for receiving interrupt requests of a first type; second interrupt receiving means coupled to the central processing unit and to a second interrupt request signal conductor for receiving interrupt requests of a second type; state determining means coupled to the first and second status bits and the first and second interrupt receiving means for determining, in response to receipt of an interrupt request by either the first or second interrupt receiving means, whether the interrupt request is of the first type or the second type, whether the first status bit is in a first state or a second state and whether the second status bit is in the first state or the second state; and register set selecting means coupled to the state determining means and to the central processing unit means for selecting, in response to receipt of an interrupt request by either the first or second interrupt receiving means, one of the first and third register subsets and one of the second and fourth register subsets for utilization by the central processing unit means, the selection by the register set selecting means is dependent upon determinations of the state determining means.

Claim 12

A digital data processor according to claim 9 wherein the register set selection means always selects the third register subset after a first interrupt request of the second type has been received and before the first interrupt request of the second type has been completed.

Claim 13

A digital data processor according to claim 10 wherein the register set selection means always selects the fourth register subset while the central processing unit means is processing an interrupt request of the second type.

Claim 14

A digital data processor according to claim 11 further comprising: next state determining means coupled to the first and second status bits and the first and second interrupt receiving means for determining, in response to receipt of an interrupt request by either the first or second interrupt receiving means, new values of the first and second status bits.

Claim 15

A digital data processor according to claim 12 further comprising: a first control bit coupled to the bus and to the register set selecting means, a state of the first control bit indicates which of the first and second register sets is presently being utilized by the central processing unit means, the central processing unit means is capable of determining the state of the first control bit independent of the register set selecting means.

Claim 16

A digital data processor according to claim 12 wherein the states of the first and second status bits, taken together, indicate one of: that no interrupt request of the second type has been received that has not been completed; that only one interrupt request of the second type has been received and that a most recent interrupt request received was of the second type; that more than one interrupt request of the second type has been received and that a most recent interrupt request received was of the second type; and that at least one of the second type of interrupt request has been received and that a most recent interrupt request received was of the first type.

Claim 17

A digital data processor according to claim 12 further comprising: a third status bit coupled to the bus; and wherein the first, second and third status bits, taken together, indicate one of: that no interrupt request of the second type has been received that has not been completed; that only one interrupt request of the second type has been received and that a most recent interrupt request received was of the second type; that more than one interrupt request of the second type has been received and that a most recent interrupt request received was of the second type; and that at least one of the second type of interrupt request has been received and that a most recent interrupt request received was of the first type.

Claim 18

A digital data processor according to claim 15 wherein the first status bit, if in the first state, indicates: that no interrupt request of the second type has been received that has not been completed.

Claim 19

A digital data processor according to claim 15 wherein the second status bit, if in the second state, indicates: that only one interrupt request of the second type has been received and that a most recent interrupt request received was of the second type.

Claim 20

A digital data processor according to claim 15 wherein the third status bit, if in the second state, indicates: that a most recent interrupt request received and not completed was of the second type.

Claim 23

A method according to claim 19 further comprising the steps of: setting and clearing the first and second status bits dependent upon: whether an interrupt presently being processed is of the second type and is the only such interrupt request of the second type which has been received and not completed.

Claim 24

A method according to claim 20 wherein the step of selecting one of the first register set and the second register set further comprises the steps of: selecting one of a first and third register subsets and one of a second and fourth register subsets.

Claim 25

A method according to claim 21 wherein the step of selecting one of the first register set and the second register set further comprises the step of: always selecting the third register subset after a first interrupt request of the second type has been received and before the first interrupt request of the second type has been completed.

Claim 26

A method according to claim 21 wherein the step of selecting one of the first register set and the second register set further comprises the step of: always selecting the fourth register subset while the central processing unit means is processing an interrupt request of the second type.