Method and apparatus for testing a memory

Claim 1

A method for testing a memory in an information processing system which includes a processor unit and at least one memory device having a built-in memory test capability, the method comprising the steps of: conducting a test using the built-in memory test capability; and conducting an additional test using normal write/read operations of the memory performed by the processor unit, the additional test being performed with a limited number of addresses and data patterns of the memory to be tested.

Claim 2

A method for testing a memory in an information processing system which includes a processor unit and at least one memory device having a built-in memory test capability, the method comprising the steps of: conducting a test using the built-in memory test capability; and conducting an additional test using normal write/read operations of the memory performed by the processor unit, the additional test being performed with a limited number of addresses and data patterns of the memory to be tested.

Claim 3

An apparatus for testing a memory under control of a processor wherein the memory includes at least one memory device having a built-in memory test function, the apparatus comprising: control means for controlling the built-in memory test function of the at least one memory device; judging means for judging a result of a memory test using the built-in memory test function; accessing means for accessing the memory by the processor; an address register for storing an address of the memory to be tested; a data register for storing write data or read data; and switching means for switching between a first memory access route for normal accessing by the processor and a second memory access route for accessing by said control means.

Claim 4

An apparatus for testing a memory under control of a processor wherein the memory includes at least one memory device having a built-in memory test function, the apparatus comprising: control means for controlling the built-in memory test function of the at least one memory device; judging means for judging a result of a memory test using the built-in memory test function; accessing means for accessing the memory by the processor; an address register for storing an address of the memory to be tested; a data register for storing write data or read data; and switching means for switching between a first memory access route for normal accessing by the processor and a second memory access route for accessing by said control means.

Claim 7

A method for testing a memory unit mounted on an information processing system which includes a processor unit, said memory unit including at least one memory device having a built-in memory test capability, said at least one memory device including address locations and data buses, the method comprising the steps of: testing said memory unit at every address location thereof by using the built-in memory test capability, while said at least one memory device is mounted on the information processing system; and testing said memory unit at said address locations thereof by using normal write/read operations performed by said processor unit in the information processing system while said at least one memory device is mounted on the information processing system.

Claim 8

A method for testing a memory unit mounted on an information processing system which includes a processor unit, said memory unit including at least one memory device having a built-in memory test capability, said at least one memory device including address locations and data buses, the method comprising the steps of: testing said memory unit at every address location thereof by using the built-in memory test capability, while said at least one memory device is mounted on the information processing system; and testing said memory unit at said address locations thereof by using normal write/read operations performed by said processor unit in the information processing system while said at least one memory device is mounted on the information processing system.