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US5023887A
Expired / Lapsed
US
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Data transmission system using spread spectrum communication
Assignee: Tokyo Keiki Inc
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Filing: 1990-02-12
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Granted: 1991-06-11
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Expires: 2010-02-12
Abstract
Abstract In response to a bit transfer request from one of two units, bit data is transmitted bit by bit from the other of the two units. The unit on the transmission side for transmitting the bit data has an M-series generator. In response to bit 1, a first M 0 -series signal of a 63-word length is generated. In response to bit 0, a second M 0 -series signal in which the series start position is set to the intermediate position of the first M 0 -series signal, although the signal is the same M 0 -series signal of the 63-word length, is generated. The unit on the reception side has previously stored the first and second M 0 -series signals on the transmission side as reference signals, and calculates the correlations between the two reference signals and the reception signal, and demodulates the data bit corresponding to the reference signal having a larger correlation value.
Inventors
- 👤 Kunihiko Takeuchi
- 👤 Masao Oba
- 👤 Shinichi Horinouchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:38
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4906; H04L25/4908
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
258 words
A data transmission system using a spread spectrum communication technique, comprising: a first unit for requesting a bit transfer; and a second unit for transmitting serial data bit by bit each time said second unit receives a bit transfer request from said first unit; wherein said second unit has an M-series generating means for generating a first M-series signal having a predetermined word length in correspondence with one of two binary logic values of one bit of said serial data and for generating a second M-series signal in which a series start position differs although it is the same M-series signal as the first M-series signal in correspondence with the other of said two binary logic values of said one bit of said serial data; and wherein said first unit has: a first correlation calculating means for calculating a correlation between a reference signal which has previously been stored and is the same as said first M-series signal and a reception signal output from said second unit; a second correlation calculating means for calculating a correlation between a reference signal which has previously been stored and is the same as said second M-series signal and said reception signal output from said second unit, and a discriminating means for comparing magnitudes of a first correlation value which was calculated by said first correlation calculating means and a second correlation value which was calculated by said second correlation calculating means, for thereby discriminating the logic value of the data bit of said reception signal, and for outputting said logic values.
Claim 2
Dependent Claim
258 words
A data transmission system using a spread spectrum communication technique, comprising: a first unit for requesting a bit transfer; and a second unit for transmitting serial data bit by bit each time said second unit receives a bit transfer request from said first unit; wherein said second unit has an M-series generating means for generating a first M-series signal having a predetermined word length in correspondence with one of two binary logic values of one bit of said serial data and for generating a second M-series signal in which a series start position differs although it is the same M-series signal as the first M-series signal in correspondence with the other of said two binary logic values of said one bit of said serial data; and wherein said first unit has: a first correlation calculating means for calculating a correlation between a reference signal which has previously been stored and is the same as said first M-series signal and a reception signal output from said second unit; a second correlation calculating means for calculating a correlation between a reference signal which has previously been stored and is the same as said second M-series signal and said reception signal output from said second unit, and a discriminating means for comparing magnitudes of a first correlation value which was calculated by said first correlation calculating means and a second correlation value which was calculated by said second correlation calculating means, for thereby discriminating the logic value of the data bit of said reception signal, and for outputting said logic values.
Claim 3
Dependent Claim
36 words
A system according to claim 1, wherein said M-series generating means of said second unit generates said second M-series signal in which an intermediate position of said first M-series signal is set to a start position.
Claim 4
Dependent Claim
126 words
A system according to claim 1, wherein said M-series generating means comprises: a shift register having shift stages of the number (N) corresponding to a predetermined word length (2 N -1); a gate circuit for calculating an exclusive OR of outputs of two predetermined shift stages in said shift register and for supplying a result of the calculation to the input shift stages; and a loading circuit for loading an initial value to generate an M-series signal having a predetermined arrangement order to said shift register when one of said two binary logic values of the data bits is transmitted and loading another initial value to generate the same M-series signal from an intermediate position when the other logic value of the data bits is transmitted.
Claim 5
Dependent Claim
113 words
A system according to claim 3, wherein, when the number N of shift stages of said shift registers is set to 6 and the exclusive OR of the outputs of said two shift stages of said shift register is calculated by said gate circuit and is supplied to the input shift stage so that said shift register generates an M 0 -series signal, said loading circuit loads the shift bits of b.sub.5 b.sub.4 b.sub.3 b.sub.2 b.sub.1 b.sub.0 =111111 in correspondence with one of the logic values of the data bits and loads the shift bits of b.sub.5 b.sub.4 b.sub.3 b.sub.2 b.sub.1 b.sub.0 =101111 in correspondence the other logic value of the data bits.
Claim 6
Dependent Claim
108 words
A system according to claim 1, wherein said first correlation calculating means comprises: an A/D converter for sampling the reception signal and A/D converting the sampled signal into digital data; a shift register for storing the converted data of said A/D converter by at least an amount of only one word length of said first M-series signal; a group of multipliers for multiplying each of the data stored in the shift register with each of the values of the first M-series signals of the same number which have previously been stored in a memory; and an adder for calculating the sum of outputs of said group of multipliers.
Claim 7
Dependent Claim
107 words
A system according to claim 1, wherein said second correlation means comprises: an A/D converter for sampling the reception signal and A/D converting the sampled signal into digital data; a shift register for storing the converted data of said A/D converter by at least an amount of only one word length of said second M-series signal; a group of multipliers for multiplying each of the data stored in the shift register with each of the values of the second M-series signals of the same number which have previously been stored in a memory; and an adder for calculating the sum of outputs of said group of multipliers.
Claim 8
Dependent Claim
49 words
A system according to claim 1, wherein the first and second units include a pair of induction coils for effecting a signal transmission of the transfer request of the data bits and another pair of induction coils for transmitting the bit data in response to the bit transfer request.
Claim 9
Dependent Claim
51 words
A system according to claim 1, wherein said first unit is a reader/writer for writing or reading data in response to a command from a host, and said second unit is a portable memory module for writing or reading data into/from a memory in accordance with an access from the reader/writer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-10 | 1994-12-10 | 1995-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-10 | 1998-12-10 | 1999-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-10 | 2002-12-10 | 2003-06-11 | $7700.00 | Window Closed / Lapsed |