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US5023189A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of thermal balancing RF power transistor array

Assignee: ZOLTAR ACQUISITION Inc A Corp OF NORTH CAROLINA
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Filing: 1990-05-04
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Granted: 1991-06-11
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Expires: 2010-05-04
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Abstract

Abstract Thermal balance in an array of RF transistor cells in which all transistors are connected in parallel is obtained by interconnecting the transistors to array contacts by means of discrete wire leads. The array is electrically tested and a temperature distribution in the array is obtained. Thereafter, the wire leads are varied in length and height above the plane of the array to improve temperature distribution during test. The steps are repeated as necessary to obtain a desired temperature balance in the array.

Inventors

  • 👤 Howard D. Bartlow

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 17:49
CPC Classifications
H; H10; H10W; H10W72/00; H10W44/00; H10W44/20; H10W44/226; H10W72/50; H10W72/541; H10W72/5445; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49004

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 103 words
A method of thermally balancing an array of RF bipolar transistors, connected in parallel, each transistor having emitter, base and collector contacts, said method comprising the steps of a) providing emitter, base and collector array contacts. b) interconnecting at least one of said emitter, base and collector contacts of said transistors to the respective emitter, base and collector array contacts by a plurality of wire leads, c) obtaining a measure of temperature distribution of said array of RF transistors during electrical test, and d) altering the lengths and heights of selected wire leads to improve temperature distribution in said array during electrical test.
Claim 2
Independent Claim 103 words
A method of thermally balancing an array of RF bipolar transistors, connected in parallel, each transistor having emitter, base and collector contacts, said method comprising the steps of a) providing emitter, base and collector array contacts. b) interconnecting at least one of said emitter, base and collector contacts of said transistors to the respective emitter, base and collector array contacts by a plurality of wire leads, c) obtaining a measure of temperature distribution of said array of RF transistors during electrical test, and d) altering the lengths and heights of selected wire leads to improve temperature distribution in said array during electrical test.
Claim 3
Dependent Claim 28 words
The method as defined by claim 1 and further including e) repeating steps b), c), and d) as necessary to obtain a desired temperature balance in said array.
Claim 4
Dependent Claim 54 words
In thermally balancing an array of RF transistors connected in parallel, the method of interconnecting said transistors to array contacts by means of a plurality of discrete wire leads, determining the temperature distribution of said array during electrical test, and varying said plurality of discrete wire leads to improve thermal balance of said array.
Claim 5
Dependent Claim 54 words
In thermally balancing an array of RF transistors connected in parallel, the method of interconnecting said transistors to array contacts by means of a plurality of discrete wire leads, determining the temperature distribution of said array during electrical test, and varying said plurality of discrete wire leads to improve thermal balance of said array.
Claim 6
Dependent Claim 18 words
The method as defined by claim 3 wherein said plurality of discrete wire leads is varied in length.
Claim 7
Dependent Claim 24 words
The method as defined by claim 4 wherein said plurality of wire leads are further varied in height above the plane of said array.
Claim 8
Dependent Claim 23 words
The method as defined by claim 3 wherein said plurality of wire leads are varied in height above the plane of said array.
Claim 9
Dependent Claim 24 words
The method as defined by claim 3 wherein the step of varying said plurality of wire leads adjusts current to said transistors more uniformly.

References Cited (Backward Citations)

US4356379A Cited
US4246697A Cited
US4881029A Cited
US4937203A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-06-10 1994-12-10 1995-06-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-06-10 1998-12-10 1999-06-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-06-10 2002-12-10 2003-06-11 $7700.00 Window Closed / Lapsed

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