US5014231A
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US
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Randomized digital/analog converter direct digital synthesizer
Assignee: The AT&T MVPD Group LLC
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Filing: 1989-07-17
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Granted: 1991-05-07
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Expires: 2009-07-17
Abstract
Abstract A sine output or phase interpolation direct digital synthesizer for use in satellite programs having a random or pseudorandom code generator for summing a random digital word whose value ranges from zero to just under the least significant bit of a digital-to-analog converter with the current register value normally sent to the converter for reducing the spurious sidebands associated with the finite resolution of the converter within the synthesizer, the sum being truncated to the resolution of the converter and for controlling the converter, the spurious sidebands being reduced by randomization of the periodic behavior associated with the truncation process while lowering the total phase noise.
Inventors
- 👤 Victor S. Reinhardt
- 👤 Kim V. Gould
- 👤 Kevin M. McNab
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:43
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/0321; G06F1/0328; G06F2211/00; G06F2211/902
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
182 words
A randomized synthesizing apparatus for reducing the spurious sidebands of a synthesized signal comprising, in combination: accumulating means within said synthesizing apparatus, receiving an incremental input signal, for generating a phase angle and for providing a periodic output register value in synchronism with said phase angle; mathematical reference means connected to said accumulating means for receiving said periodic output register value and for providing a mathematical reference for said register value; noise generating means within said synthesizing apparatus for generating a random word; summing means in communication with said mathematical reference means and said noise generating means for summing said mathematical reference of said register value and said random word to provide a sum output digital signal, said sum output digital signal being truncated; and converting means connected to said summing means for receiving said truncated sum output digital signal and converting said truncated sum for a digital signal to an analog signal, said random word converting said spurious sidebands to broad band phase noise by destroying the coherence of said sidebands and by randomizing the periodic behavior of said truncation process.
Claim 2
Dependent Claim
182 words
A randomized synthesizing apparatus for reducing the spurious sidebands of a synthesized signal comprising, in combination: accumulating means within said synthesizing apparatus, receiving an incremental input signal, for generating a phase angle and for providing a periodic output register value in synchronism with said phase angle; mathematical reference means connected to said accumulating means for receiving said periodic output register value and for providing a mathematical reference for said register value; noise generating means within said synthesizing apparatus for generating a random word; summing means in communication with said mathematical reference means and said noise generating means for summing said mathematical reference of said register value and said random word to provide a sum output digital signal, said sum output digital signal being truncated; and converting means connected to said summing means for receiving said truncated sum output digital signal and converting said truncated sum for a digital signal to an analog signal, said random word converting said spurious sidebands to broad band phase noise by destroying the coherence of said sidebands and by randomizing the periodic behavior of said truncation process.
Claim 3
Dependent Claim
14 words
The randomized synthesizing apparatus of claim 1 wherein said accumulating means comprises in accumulator.
Claim 4
Dependent Claim
36 words
The randomized synthesizing apparatus of claim 2 wherein said accumulator comprises a storage register and an adder operatively connected to said storage register for adding said incremental input value to contents stored in said storage register.
Claim 5
Dependent Claim
14 words
The randomized synthesizing apparatus of claim 3 wherein said adder is an N-bit adder.
Claim 6
Dependent Claim
16 words
The randomized synthesizing apparatus of claim 3 wherein said storage register is an N-bit storage register.
Claim 7
Dependent Claim
17 words
The randomized synthesizing apparatus of claim 1 wherein said mathematical reference means is a sine look-up table.
Claim 8
Dependent Claim
17 words
The randomized synthesizing apparatus of claim 6 wherein said sine look-up table comprises a read only memory.
Claim 9
Dependent Claim
17 words
The randomized synthesizing apparatus of claim 6 wherein said sine look-up table comprises a random access memory.
Claim 10
Dependent Claim
17 words
The randomized synthesizing apparatus of claim 1 wherein said noise generating means comprises a random noise generator.
Claim 11
Dependent Claim
17 words
The randomized synthesizing apparatus of claim 1 wherein said noise generating means comprises a pseudorandom noise generator.
Claim 12
Dependent Claim
14 words
The randomized synthesizing apparatus of claim 1 wherein said summing means comprises an adder.
Claim 13
Dependent Claim
24 words
The randomized synthesizing apparatus of claim 11 wherein said mathematical reference of said register value is equal to the sine of said register value.
Claim 14
Dependent Claim
49 words
The randomized synthesizing apparatus of claim 12 wherein said converting means has a predetermined bit resolution with a least significant bit, and said random word is a digital number identified by (x) and ranging in value from zero to the least significant bit of said converting means minus one.
Claim 15
Dependent Claim
32 words
The randomized synthesizing apparatus of claim 13 wherein said adder provides said sum output digital signal, said output digital signal being the sum of the sine of said register value and (x).
Claim 16
Dependent Claim
19 words
The randomized synthesizing apparatus of claim 1 wherein said truncated sum of said summing means is N-bits in length.
Claim 17
Dependent Claim
15 words
The randomized synthesizing apparatus of claim 1 wherein said converting means comprises a digital-to-analog converter.
Claim 18
Dependent Claim
15 words
The randomized synthesizing apparatus of claim 1 wherein said converting means is M-bits in length.
Claim 19
Dependent Claim
15 words
The randomized synthesizing apparatus of claim 1 wherein said analog signal is an electrical voltage.
Claim 20
Dependent Claim
34 words
The randomized synthesizing apparatus of claim 1 wherein said means for converting has a bit resolution of M bits, and said broad band phase noise is reduced by a factor of (2 -M ).
Claim 21
Dependent Claim
19 words
The randomized synthesizing apparatus of claim 1 wherein said apparatus is small in size, lightweight, and minimizes power consumption.
Claim 22
Dependent Claim
180 words
A randomized digital-to-analog converter direct digital synthesizer for reducing the spurious sidebands of a synthesized signal comprising, in combination: an accumulator included within said synthesizer, receiving an incremental input signal, for generating a phase angle and for providing a periodic output register value in synchronism with said phase angle; a read only memory connected to said accumulator, receiving said periodic output register value, and for providing a mathematical sine equivalent for said register value; a noise generator included within said synthesizer for generating a random digital word; an adder in communication with said read only memory and said noise generator for summing said mathematical sine equivalent of said register value and said random digital word to provide a sum output, said sum being truncated; and a digital-to-analog converter connected to said added for converting said truncated sum from a digital signal to an analog signal, for providing an output voltage, said random digital word converting said spurious sidebands to broad band phase noise by destroying the coherency of said sidebands and by randomizing the periodic behavior of said truncation process.
Claim 23
Dependent Claim
180 words
A randomized digital-to-analog converter direct digital synthesizer for reducing the spurious sidebands of a synthesized signal comprising, in combination: an accumulator included within said synthesizer, receiving an incremental input signal, for generating a phase angle and for providing a periodic output register value in synchronism with said phase angle; a read only memory connected to said accumulator, receiving said periodic output register value, and for providing a mathematical sine equivalent for said register value; a noise generator included within said synthesizer for generating a random digital word; an adder in communication with said read only memory and said noise generator for summing said mathematical sine equivalent of said register value and said random digital word to provide a sum output, said sum being truncated; and a digital-to-analog converter connected to said added for converting said truncated sum from a digital signal to an analog signal, for providing an output voltage, said random digital word converting said spurious sidebands to broad band phase noise by destroying the coherency of said sidebands and by randomizing the periodic behavior of said truncation process.
Claim 24
Independent Claim
147 words
A method for the randomization of spurious sidebands in a sine output direct digital synthesizer, said method comprising the steps of: generating a phase angle from a periodic incremental input signal to an accumulator; providing a periodic output register value from said accumulator, said register value in synchronism with said phase angle; connecting a read only memory to said accumulator for receiving said periodic output register value and providing a mathematical sine equivalent value; generating a random digital word for converting said spurious sidebands to broad band phase noise; summing said mathematical sine equivalent and said random digital word to provide a sum output, and truncating said sum for destroying the coherence of said sidebands; and converting said truncated sum from a digital signal to an analog signal for providing an output voltage, said spurious sidebands being reduced by randomizing the periodic behavior of said truncation process.
Claim 25
Independent Claim
147 words
A method for the randomization of spurious sidebands in a sine output direct digital synthesizer, said method comprising the steps of: generating a phase angle from a periodic incremental input signal to an accumulator; providing a periodic output register value from said accumulator, said register value in synchronism with said phase angle; connecting a read only memory to said accumulator for receiving said periodic output register value and providing a mathematical sine equivalent value; generating a random digital word for converting said spurious sidebands to broad band phase noise; summing said mathematical sine equivalent and said random digital word to provide a sum output, and truncating said sum for destroying the coherence of said sidebands; and converting said truncated sum from a digital signal to an analog signal for providing an output voltage, said spurious sidebands being reduced by randomizing the periodic behavior of said truncation process.
Claim 26
Dependent Claim
168 words
A randomized synthesized apparatus for reducing the spurious sidebands of a synthesized signal comprising, in combination: accumulating means within said synthesizing apparatus, receiving an incremental input signal, for generating a phase angle and for providing a periodic output register value in synchronism with said phase angle; noise generating means within said synthesizing apparatus for generating a random word; summing means in communication with said accumulating means and said noise generating means for providing a carry pulse and for summing said periodic output register value and said random word to provide a sum output digital signal, said sum output digital signal being truncated; and delay means connected to said summing means to receive said truncated sum output digital signal and said carry pulse for delaying said carry pulse by an increment of time proportional to said truncated sum, said delayed carry pulse for converting said spurious sidebands to broad band phase noise by destroying the coherence of said sidebands and by randomizing the periodic behavior of sand truncation process.
Claim 27
Dependent Claim
168 words
A randomized synthesized apparatus for reducing the spurious sidebands of a synthesized signal comprising, in combination: accumulating means within said synthesizing apparatus, receiving an incremental input signal, for generating a phase angle and for providing a periodic output register value in synchronism with said phase angle; noise generating means within said synthesizing apparatus for generating a random word; summing means in communication with said accumulating means and said noise generating means for providing a carry pulse and for summing said periodic output register value and said random word to provide a sum output digital signal, said sum output digital signal being truncated; and delay means connected to said summing means to receive said truncated sum output digital signal and said carry pulse for delaying said carry pulse by an increment of time proportional to said truncated sum, said delayed carry pulse for converting said spurious sidebands to broad band phase noise by destroying the coherence of said sidebands and by randomizing the periodic behavior of sand truncation process.
Claim 28
Dependent Claim
14 words
The randomized synthesizing apparatus of claim 23 wherein said accumulating means comprises an accumulator.
Claim 29
Dependent Claim
36 words
The randomized synthesizing apparatus of claim 24 wherein said accumulator comprises a storage register and an adder operatively connected to said storage register for adding said incremental input value to contents stored in said storage register.
Claim 30
Dependent Claim
14 words
The randomized synthesizing apparatus of claim 25 wherein said adder is an N-bit adder.
Claim 31
Dependent Claim
16 words
The randomized synthesizing apparatus of claim 25, wherein said storage register is an N-bit storage register.
Claim 32
Dependent Claim
17 words
The randomized synthesizing apparatus of claim 23 wherein said noise generating means comprises a random noise generator.
Claim 33
Dependent Claim
17 words
The randomized synthesizing apparatus of claim 23 wherein said noise generating means comprises a pseudorandom noise generator.
Claim 34
Dependent Claim
14 words
The randomized synthesizing apparatus of claim 23 wherein said summing means comprises an adder.
Claim 35
Dependent Claim
48 words
The randomized synthesizing apparatus of claim 30 wherein said delay means has a predetermined bit resolution with a least significant bit, said random word is a digital number identified by (x) and ranging in value from zero to the least significant bit of said delay means minus one.
Claim 36
Dependent Claim
28 words
The randomized synthesizing apparatus of claim 31 wherein said adder provides said sum output digital signal, said output signal being the sum of said register value and (x).
Claim 37
Dependent Claim
19 words
The randomized synthesizing apparatus of claim 23 wherein said apparatus is small in size, lightweight, and minimizes power consumption.
Claim 38
Dependent Claim
30 words
The randomized synthesizing apparatus of claim 23 wherein said delay means has a bit resolution of M bits, and said truncated sum of said summing means is M-bits in length.
Claim 39
Dependent Claim
15 words
The randomized synthesizing apparatus of claim 23 wherein said delay means comprises a delay generator.
Claim 40
Dependent Claim
15 words
The randomized synthesizing apparatus of claim 23 wherein said delay means comprises a digitalto-phase converter.
Claim 41
Dependent Claim
15 words
The randomized synthesizing apparatus of claim 23 wherein said delay means is M-bits in length.
Claim 42
Dependent Claim
16 words
The randomized synthesizing apparatus of claim 23 wherein said delay means provides an output frequency signal.
Claim 43
Dependent Claim
33 words
The randomized synthesizing apparatus of claim 23 wherein said delay means has a bit resolution of M bits, and said broad band phase noise is reduced by a factor of (2 -M ).
Claim 44
Independent Claim
158 words
A method for the randomization of spurious sidebands in a phase interpolation direct digital synthesizer, said method comprising the steps of: generating a phase angle from a periodic incremental input signal to an accumulator; providing a periodic output register value from said accumulator, said register value in synchronism with said phase angle; generating a random digital word for converting said spurious sidebands to broad band phase noise; summing said periodic output register value with said random digital word to provide a sum output and a carry pulse, said sum being truncated for destroying the coherence of said sidebands; receiving said truncated sum and said carry pulse in a delay generator operative to produce a delay of said carry pulse responsive to said truncated sum by an increment of time proportional to said truncated sum; and generating a synthesized signal from said delayed carry pulse, whereby said spurious sidebands are randomized by randomizing the delay of said carry pulse.
Claim 45
Independent Claim
158 words
A method for the randomization of spurious sidebands in a phase interpolation direct digital synthesizer, said method comprising the steps of: generating a phase angle from a periodic incremental input signal to an accumulator; providing a periodic output register value from said accumulator, said register value in synchronism with said phase angle; generating a random digital word for converting said spurious sidebands to broad band phase noise; summing said periodic output register value with said random digital word to provide a sum output and a carry pulse, said sum being truncated for destroying the coherence of said sidebands; receiving said truncated sum and said carry pulse in a delay generator operative to produce a delay of said carry pulse responsive to said truncated sum by an increment of time proportional to said truncated sum; and generating a synthesized signal from said delayed carry pulse, whereby said spurious sidebands are randomized by randomizing the delay of said carry pulse.
Claim 46
Dependent Claim
163 words
A randomized digital-to-analog converter direct digital synthesizer for reducing the spurious sidebands of a synthesized signal comprising, in combination: an accumulator included within said synthesizer, receiving an incremental input signal, for generating a phase angle and for providing a periodic output register value in synchronism with said phase angle; a noise generator included within said synthesizer for generating a random digital word; an adder in communication with said accumulator and said noise generator for providing a carry pulse and for summing said periodic output register value and said random digital word to provide a sum output, said sum being truncated; and a delay generator connected to said adder, for receiving said truncated sum and said carry pulse, for delaying said carry pulse by an increment of time proportional to said truncated sum, said delayed carry pulse for converting said spurious sidebands to broad band phase noise by destroying the coherence of said sidebands and by randomizing the periodic behavior of said truncation process.
Claim 47
Dependent Claim
163 words
A randomized digital-to-analog converter direct digital synthesizer for reducing the spurious sidebands of a synthesized signal comprising, in combination: an accumulator included within said synthesizer, receiving an incremental input signal, for generating a phase angle and for providing a periodic output register value in synchronism with said phase angle; a noise generator included within said synthesizer for generating a random digital word; an adder in communication with said accumulator and said noise generator for providing a carry pulse and for summing said periodic output register value and said random digital word to provide a sum output, said sum being truncated; and a delay generator connected to said adder, for receiving said truncated sum and said carry pulse, for delaying said carry pulse by an increment of time proportional to said truncated sum, said delayed carry pulse for converting said spurious sidebands to broad band phase noise by destroying the coherence of said sidebands and by randomizing the periodic behavior of said truncation process.
Claim 48
Dependent Claim
163 words
A randomized digital-to-analog converter direct digital synthesizer for reducing the spurious sidebands of a synthesized signal comprising, in combination: an accumulator included within said synthesizer, receiving an incremental input signal, for generating a phase angle and for providing a periodic output register value in synchronism with said phase angle; a noise generator included within said synthesizer for generating a random digital word; an adder in communication with said accumulator and said noise generator for providing a carry pulse and for summing said periodic output register value and said random digital word to provide a sum output, said sum being truncated; and a digital-to-phase converter connected to said adder, for receiving said truncated sum and said carry pulse, for delaying said carry pulse by an increment of time proportional to said truncated sum, said delayed carry pulse for converting said spurious sidebands to broad band phase noise by destroying the coherence of said sidebands and by randomizing the periodic behavior of said truncation process.
Claim 49
Dependent Claim
163 words
A randomized digital-to-analog converter direct digital synthesizer for reducing the spurious sidebands of a synthesized signal comprising, in combination: an accumulator included within said synthesizer, receiving an incremental input signal, for generating a phase angle and for providing a periodic output register value in synchronism with said phase angle; a noise generator included within said synthesizer for generating a random digital word; an adder in communication with said accumulator and said noise generator for providing a carry pulse and for summing said periodic output register value and said random digital word to provide a sum output, said sum being truncated; and a digital-to-phase converter connected to said adder, for receiving said truncated sum and said carry pulse, for delaying said carry pulse by an increment of time proportional to said truncated sum, said delayed carry pulse for converting said spurious sidebands to broad band phase noise by destroying the coherence of said sidebands and by randomizing the periodic behavior of said truncation process.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-06 | 1994-11-05 | 1995-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-06 | 1998-11-05 | 1999-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-06 | 2002-11-05 | 2003-05-07 | $7700.00 | Window Closed / Lapsed |