Digital sine conversion circuit for use in direct digital synthesizers

Claim 2

A digital sine conversion circuit, comprising: means for dividing a sine wave quadrant into a plurality of coarse phase angle intervals; means for dividing each of said coarse intervals into a plurality of intermediate phase angle intervals; means for storing an amplitude value associated with each coarse phase phase angle interval; means for storing a slope value associated with each intermediate phase angle interval; means for storing a carry value associated with each intermediate phase angle interval; means for providing the phase angle value at each intermediate phase angle interval; means for multiplying the phase angle value by the slope value at each intermediate phase angle interval to produce a first intermediate value; means for adding the carry value at each intermediate phase angle interval to the first intermediate value to produce a second intermediate value; and means for adding the coarse value to said second intermediate value to produce a sine wave amplitude value at each intermediate phase angle interval.

Claim 3

A digital sine conversion circuit as described in claim 1 further including means for 2's complementing the sine wave amplitude value.

Claim 4

A digital sine conversion circuit as described in claim 1 wherein said values in said carry value storing means have the value 1 for a first portion of an intermediate phase angle intervals and a value 0 for a second portion of the intermediate phase angle intervals.

Claim 5

A digital sine conversion circuit as described in claim 3 wherein said first portion of said intermediate phase angle intervals occupies greater than one half of said intermediate phase angle intervals.

Claim 6

A digital sine conversion circuit as described in claim 4 wherein said first portion of said intermediate phase angle intervals occupies three-fourths of said intermediate phase angle intervals.

Claim 7

A digital sine conversion circuit as described in claim 5 wherein said first portion precedes said second portion in time.

Claim 8

A digital sine conversion circuit as described in claim 5 wherein said first portion follows said second portion in time.

Claim 9

A digital sine conversion circuit as described in claim 5 wherein said carry value storing means contains two digital bits.

Claim 10

A digital sine conversion circuit as described in claim 5 wherein a first of said bits determines whether to add the value 1 at said first intermediate value intervals and the second of said bits determines whether the value 1 is added at said first intermediate value intervals at the first or the second three-fourths of said intermediate phase angle values.

Claim 11

A digital sine conversion circuit, comprising: means for dividing a sine wave quadrant into a plurality of coarse phase angle intervals; means for dividing each of said coarse intervals into a plurality of intermediate phase angle intervals; first read-only-memory for storing an amplitude value associated with each coarse phase angle interval; second read-only-memory for storing a slope value associated with each intermediate phase angle interval; third read-only-memory for storing a carry value associated with each intermediate phase angle interval; means for providing the phase angle value at each intermediate phase angle interval; means for multiplying the phase angle value by the slope value at each intermediate phase angle interval to produce a first intermediate value; an adder adding the carry value at each intermediate phase angle interval to the first intermediate value to produce a second intermediate value; means for restricting addition of said carry value at either the first or the second three-fourths of said intermediate phase angle intervals; means for determining which of the first and second three-fourths of said phase angle intervals to which said carry bit will be added; and means for adding the coarse value to said second intermediate value to produce a sine wave amplitude value at each intermediate phase angle interval.

Claim 12

A digital sine conversion circuit, comprising: means for dividing a sine wave quadrant into a plurality of coarse phase angle intervals; means for dividing each of said coarse intervals into a plurality of intermediate phase angle intervals; first read-only-memory for storing an amplitude value associated with each coarse phase angle interval; second read-only-memory for storing a slope value associated with each intermediate phase angle interval; third read-only-memory for storing a carry value associated with each intermediate phase angle interval; means for providing the phase angle value at each intermediate phase angle interval; means for multiplying the phase angle value by the slope value at each intermediate phase angle interval to produce a first intermediate value; an adder adding the carry value at each intermediate phase angle interval to the first intermediate value to produce a second intermediate value; means for restricting addition of said carry value at either the first or the second three-fourths of said intermediate phase angle intervals; means for determining which of the first and second three-fourths of said phase angle intervals to which said carry bit will be added; and means for adding the coarse value to said second intermediate value to produce a sine wave amplitude value at each intermediate phase angle interval.