Method and apparatus for testing very large scale integrated memory circuits

Claim 1

A system for testing a high density memory on a chip, comprising; a high density memory with plural memory cells formed on a single semiconductor chip; a plurality of bit lines connected to the memory cells of said high density memory; at least one parallel signature analyzer disposed on said chip adjacent the high density memory; said parallel signature analyzer including: means coupled to said bit lines for selectively applying signals onto said bit lines to be written into the memory cells of said high density memory; means for selectively reading memory states of the memory cells of said high density memory; and means responsive to said read memory states for developing a signature from the memory states read for indicating whether the selectively applied signals were properly written into and read from the memory cells of said high density memory wherein said parallel signature analyzer comprises a multiple input linear feedback shift register wherein said shift register comprises a plurality of flip-flops, each having an input connected to a bit line of a respective one of said memory elements through an exclusive-OR gate and to an output of a preceding flip-flop through said exclusive-OR gate.

Claim 2

A system for testing a high density memory on a chip, comprising; a high density memory with plural memory cells formed on a single semiconductor chip; a plurality of bit lines connected to the memory cells of said high density memory; at least one parallel signature analyzer disposed on said chip adjacent the high density memory; said parallel signature analyzer including: means coupled to said bit lines for selectively applying signals onto said bit lines to be written into the memory cells of said high density memory; means for selectively reading memory states of the memory cells of said high density memory; and means responsive to said read memory states for developing a signature from the memory states read for indicating whether the selectively applied signals were properly written into and read from the memory cells of said high density memory wherein said parallel signature analyzer comprises a multiple input linear feedback shift register wherein said shift register comprises a plurality of flip-flops, each having an input connected to a bit line of a respective one of said memory elements through an exclusive-OR gate and to an output of a preceding flip-flop through said exclusive-OR gate.

Claim 10

The method of testing a memory chip of the type having at least one array of memory elements formed thereon, comprising: providing a memory chip of the type having at least one array of memory elements formed thereon, providing a parallel signature analyzer on said chip for each of said at least one array, operable to selectively apply signals to be written into selected memory elements in one mode, to selectively read the contents of said memory elements in another mode, and to generate a signature from the contents read to indicate whether the applied signals were properly written into and read from said memory elements; and providing means for selecting the operating mode of said parallel signature analyzer wherein said step of providing a parallel signature analyzer comprises providing a multiple input linear feedback shift register into said chip for each said at least one array of memory elements, wherein said step of providing a shift register comprises forming into said chip a plurality of flip-flops, each having an input connected to a bit line of a respective one of said memory elements through an exclusive-OR gate and to an output of a preceding flip-flop through said exclusive-OR gate.

Claim 11

The method of testing a memory chip of the type having at least one array of memory elements formed thereon, comprising: providing a memory chip of the type having at least one array of memory elements formed thereon, providing a parallel signature analyzer on said chip for each of said at least one array, operable to selectively apply signals to be written into selected memory elements in one mode, to selectively read the contents of said memory elements in another mode, and to generate a signature from the contents read to indicate whether the applied signals were properly written into and read from said memory elements; and providing means for selecting the operating mode of said parallel signature analyzer wherein said step of providing a parallel signature analyzer comprises providing a multiple input linear feedback shift register into said chip for each said at least one array of memory elements, wherein said step of providing a shift register comprises forming into said chip a plurality of flip-flops, each having an input connected to a bit line of a respective one of said memory elements through an exclusive-OR gate and to an output of a preceding flip-flop through said exclusive-OR gate.