US4594657A
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Semaphore for memory shared by two asynchronous microcomputers
Assignee: Motorola Solutions Inc
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Filing: 1983-04-22
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Granted: 1986-06-10
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Expires: 2003-04-22
Abstract
Abstract An improved semaphore is described that arbitrates the access of a memory shared by first and second microcomputers operating asynchronously at the same speed or at different speeds. The semaphore includes a semaphore flip-flop producing a binary semaphore signal indicating whether or not the semaphore is owned, and an ownership flip-flop producing a binary ownership signal indicating which of the first or second microcomputers previously owned the semaphore. First gating circuitry decodes control signals from the first microcomputer and generates a read or write pulse signal. The read pulse signal from the first gating circuitry loads the semaphore signal and ownership signal into first and second flip-flops, respectively, whose outputs are applied to the data bus of the first microcomputer. Second gating circuitry decodes control signals from the second microcomputer and generates a read or write pulse signal. The read pulse signal from the second gating circuitry loads the semaphore signal and ownership signal into third and fourth flip-flops, respectively, whose outputs are applied to the data bus of the second microcomputer. If the first and second microcomputers access the semaphore simultaneously, access is granted to the second microcomputer since the output of the third flip-flop resets the first flip-flop to deny access to the first microcomputer.
Inventors
- 👤 John P. Byrns
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:49
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/167; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1652; G06F13/1663
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
501 words
Semaphore circuitry for resource means shared by first and second processing means generating first and second control signals and coupled to first and second clock signals from first and second signal sources, respectively, said semaphore circuitry comprising: first gating means coupled to the first processing means and first clock signal source for generating a first read pulse signal or a first write pulse signal in response to the first control signal and first clock signal; first storage means coupled to the first gating means and an ownership signal for storing the ownership signal in response to the first read pulse signal; second storage means coupled to the first gating means and a semaphore signal for storing the semaphore signal in response to the first read pulse signal; second gating means coupled to the second processing means and second clock signal source for generating a second read pulse signal or a second write pulse signal in response to the second control signal and second clock signal; delay means coupled to the ownership signal for generating a delayed ownership signal; third storage means coupled to the second gating means and delay means for storing the delayed ownership signal in response to the second read pulse signal; fourth storage means coupled to the second gating means and the semaphore signal for storing the semaphore signal in response to the second read pulse signal; semaphore means coupled to the first and second gating means and the second and fourth storage means for producing the semaphore signal, said semaphore signal having a first state in response to a second state of the stored semaphore signal in the second or fourth storage means, and having a second state in response to the first or second write pulse signal, where the first state of the semaphore signal indicates that the shared resource means is owned by the first or second processing means and the second state of the semaphore signal indicates that the shared resource means is not owned by either the first or second processing means; ownership means coupled to the second and fourth storage means for producing the ownership signal, said ownership signal having a first state in response to a second state of the stored semaphore signal in the fourth storage means and having a second state in response to the second state of the stored semaphore signal in the second storage means, where the first state of the ownership signal indicates that the shared resource means is owned by the second processing means and the second state of the ownership signal indicates that the shared resource means is owned by the first processing means; and the fourth storage means further being coupled to the first and second storage means for causing the first storage means to store the second state of the ownership signal and the second storage means to store the first state of the semaphore signal in response to the second state of the stored semaphore signal in the fourth storage means.
Claim 2
Dependent Claim
501 words
Semaphore circuitry for resource means shared by first and second processing means generating first and second control signals and coupled to first and second clock signals from first and second signal sources, respectively, said semaphore circuitry comprising: first gating means coupled to the first processing means and first clock signal source for generating a first read pulse signal or a first write pulse signal in response to the first control signal and first clock signal; first storage means coupled to the first gating means and an ownership signal for storing the ownership signal in response to the first read pulse signal; second storage means coupled to the first gating means and a semaphore signal for storing the semaphore signal in response to the first read pulse signal; second gating means coupled to the second processing means and second clock signal source for generating a second read pulse signal or a second write pulse signal in response to the second control signal and second clock signal; delay means coupled to the ownership signal for generating a delayed ownership signal; third storage means coupled to the second gating means and delay means for storing the delayed ownership signal in response to the second read pulse signal; fourth storage means coupled to the second gating means and the semaphore signal for storing the semaphore signal in response to the second read pulse signal; semaphore means coupled to the first and second gating means and the second and fourth storage means for producing the semaphore signal, said semaphore signal having a first state in response to a second state of the stored semaphore signal in the second or fourth storage means, and having a second state in response to the first or second write pulse signal, where the first state of the semaphore signal indicates that the shared resource means is owned by the first or second processing means and the second state of the semaphore signal indicates that the shared resource means is not owned by either the first or second processing means; ownership means coupled to the second and fourth storage means for producing the ownership signal, said ownership signal having a first state in response to a second state of the stored semaphore signal in the fourth storage means and having a second state in response to the second state of the stored semaphore signal in the second storage means, where the first state of the ownership signal indicates that the shared resource means is owned by the second processing means and the second state of the ownership signal indicates that the shared resource means is owned by the first processing means; and the fourth storage means further being coupled to the first and second storage means for causing the first storage means to store the second state of the ownership signal and the second storage means to store the first state of the semaphore signal in response to the second state of the stored semaphore signal in the fourth storage means.
Claim 3
Dependent Claim
116 words
The semaphore circuitry according to claim 1, further including means for generating a reset signal, said semaphore means being coupled to the reset means for providing the first state of the semaphore signal in response to the reset signal, said ownership means being coupled to the reset means for providing the first state of the ownership signal in response to the reset signal, said second storage means being coupled to the reset means for providing the first state of the stored semaphore signal in response to the reset signal, and said fourth storage means being coupled to the reset means for providing the first state of the stored semaphore signal in response to the reset signal.
Claim 4
Dependent Claim
117 words
The first and second semaphore circuitry according to claim 1, further including: first data bus means coupled to the first processing means; second data bus means coupled to the second processing means; and said semaphore circuitry further including: first and second switching means coupled to the first and second storage means for applying the stored ownership signal and stored semaphore signal therein, respectively, to the first data bus means in response to the first read pulse signal; and third and fourth switching means coupled to the third and fourth storage means for applying the stored ownership signal and stored semaphore signal therein, respectively, to the second data bus means in response to the second read pulse signal.
Claim 5
Dependent Claim
511 words
The semaphore circuitry according to claim 1, further including second semaphore circuitry for second resource means shared by the first and second processing means, the first and second processing means further generating third and fourth control signals, respectively, said second semaphore circuitry comprising: first gating means coupled to the first processing means and first clock signal source for generating a first read pulse signal or a first write pulse signal in response to the third control signal and first clock signal; first storage means coupled to the first gating means and an ownership signal for storing the ownership signal in response to the first read pulse signal; second storage means coupled to the first gating means and a semaphore signal for storing the semaphore signal in response to the first read pulse signal; second gating means coupled to the second processing means and second clock signal source for generating a second read pulse signal or a second write pulse signal in response to the fourth control signal and second clock signal; delay means coupled to the ownership signal for generating a delayed ownership signal; third storage means coupled to the second gating means and delay means for storing the delayed ownership signal in response to the second read pulse signal; fourth storage means coupled to the second gating means and the semaphore signal for storing the semaphore signal in response to the second read pulse signal; semaphore means coupled to the first and second gating means and the second and fourth storage means for producing the semaphore signal, said semaphore signal having a first state in response to a second state of the stored semaphore signal in the second or fourth storage means, and having a second state in response to the first or second write pulse signal, where the first state of the semaphore signal indicates that the second shared resource means is owned by the first or second processing means and the second state of the semaphore signal indicates that the second shared resource means is not owned by either the first or second processing means; ownership means coupled to the second and fourth storage means for producing the ownership signal, said ownership signal having a first state in response to a second state of the stored semaphore signal in the fourth storage means and having a second state in response to the second state of the stored semaphore signal in the second storage means, where the first state of the ownership signal indicates that the second shared resource means is owned by the second processing means and the second state of the ownership signal indicates that the second shared resource means is owned by the first processing means; and the fourth storage means further being coupled to the first and second storage means for causing the first storage means to store the second state of the ownership signal and the second storage means to store the first state of the semaphore signal in response to the second state of the stored semaphore signal in the fourth storage means.
Claim 6
Dependent Claim
125 words
The semaphore circuitry according to claim 4, further including means for generating a reset signal; and wherein, for said first and second semaphore circuitry, said semaphore means is coupled to the reset means for providing the first state of the semaphore signal in response to the reset signal, said ownership means is coupled to the reset means for providing the first state of the ownership signal in response to the reset signal, said second storage means is coupled to the reset means for providing the first state of the stored semaphore signal in response to the reset signal, and said fourth storage means is coupled to the reset means for providing the first state of the stored semaphore signal in response to the reset signal.
Claim 7
Dependent Claim
121 words
The first and second semaphore circuitry according to claim 4, further including: first data bus means coupled to the first processing means; second data bus means coupled to the second processing means; and said first and second semaphore circuitry each further including: first and second switching means coupled to the first and second storage means for applying the stored ownership signal and stored semaphore signal therein, respectively, to the first data bus means in response to the first read pulse signal; and third and fourth switching means coupled to the third and fourth storage means for applying the stored ownership signal and stored semaphore signal therein, respectively, to the second data bus means in response to the second read pulse signal.
Claim 8
Dependent Claim
531 words
The semaphore circuitry according to claim 1, further including third processing means and second semaphore circuitry for second resource means shared by the first and third processing means, the first and third processing means generating third and fourth control signals, respectively, and the third processing means being coupled to a third clock signal from a third signal source, said second semaphore circuitry comprising: first gating means coupled to the first processing means and first clock signal source for generating a first read pulse signal or a first write pulse signal in response to the third control signal and first clock signal; first storage means coupled to the first gating means and an ownership signal for storing the ownership signal in response to the first read pulse signal; second storage means coupled to the first gating means and a semaphore signal for storing the semaphore signal in response to the first read pulse signal; second gating means coupled to the third processing means and third clock signal source for generating a second read pulse signal or a second write pulse signal in response to the fourth control signal and third clock signal; delay means coupled to the ownership signal for generating a delayed ownership signal; third storage means coupled to the second gating means and delay means for storing the delayed ownership signal in response to the second read pulse signal; fourth storage means coupled to the second gating means and the semaphore signal for storing the semaphore signal in response to the second read pulse signal; semaphore means coupled to the first and second gating means and the second an fourth storage means for producing the semaphore signal, said semaphore signal having a first state in response to a second state of the stored semaphore signal in the second or fourth storage means, and having a second state in response to the first or second write pulse signal, where the first state of the semaphore signal indicates that the second shared resource means is owned by the first or third processing means and the second state of the semaphore signal indicates that the second shared resource means is not owned by either the first or third processing means; ownership means coupled to the second and fourth storage means for producing the ownership signal, said ownership signal having a first state in response to a second state of the stored semaphore signal in the fourth storage means and having a second state in response to the second state of the stored semaphore signal in the second storage means, where the first state of the ownership signal indicates that the second shared resource means is owned by the third processing means and the second state of the ownership signal indicates that the second shared resource means is owned by the first processing means; and the fourth storage means further being coupled to the first and second storage means for causing the first storage means to store the second state of the ownership signal and the second storage means to store the first state of the semaphore signal in response to the second state of the stored semaphore signal in the fourth storage means.
Claim 9
Dependent Claim
125 words
The semaphore circuitry according to claim 7, further including means for generating a reset signal; and wherein, for said first and second semaphore circuitry, said semaphore means is coupled to the reset means for providing the first state of the semaphore signal in response to the reset signal, said ownership means is coupled to the reset means for providing the second state of the ownership signal in response to the reset signal, said second storage means is coupled to the reset means for providing the first state of the stored semaphore signal in response to the reset signal, and said fourth storage means is coupled to the reset means for providing the first state of the stored semaphore signal in response to the reset signal.
Claim 10
Dependent Claim
213 words
The first and second semaphore circuitry according to claim 7, further including: first data bus means coupled to the first processing means; second data bus means coupled to the second processing means; third data bus means coupled to the third processing means; said first semaphore circuitry further including: first and second switching means coupled to the first and second storage means for applying the stored ownership signal and stored semaphore signal therein, respectively, to the first data bus means in response to the first read pulse signal; and third and fourth switching means coupled to the third and fourth storage means for applying the stored ownership signal and stored semaphore signal therein, respectively, to the second data bus means in response to the second read pulse signal; and said second semaphore circuitry further including: first and second switching means coupled to the first and second storage means for applying the stored ownership signal and stored semaphore signal therein, respectively, to the first data bus means in response to the first read pulse signal; and third and fourth switching means coupled to the third and fourth storage means for applying the stored ownership signal and stored semaphore signal therein, respectively, to the third data bus means in response to the second read pulse signal.
Claim 11
Dependent Claim
483 words
Semaphore circuitry for a resource shared by first and second computers generating first and second control signals and coupled to first and second clock signals from first and second signal sources, respectively, said semaphore circuitry comprising: first gating circuitry coupled to the first computer and first clock signal source for generating a first read pulse signal or a first write pulse signal in response to the first control signal and first clock signal; a first flip-flop coupled to the first gating circuitry and an ownership signal for storing the ownership signal in response to the first read pulse signal; a second flip-flop coupled to the first gating circuitry and a semaphore signal for storing the semaphore signal in response to the first read pulse signal; second gating circuitry coupled to the second computer and second clock signal source for generating a second read pulse signal or a second write pulse signal in response to the second control signal and second clock signal; delay circuitry coupled to the ownership signal for generating a delayed ownership signal; a third flip-flop coupled to the second gating circuitry and delay circuitry for storing the delayed ownership signal in response to the second read pulse signal; a fourth flip-flop coupled to the second gating circuitry and the semaphore signal for storing the semaphore signal in response to the second read pulse signal; a semaphore flip-flop coupled to the first and second gating circuitry and the second and fourth flip-flops for producing the semaphore signal, said semaphore signal having a first state in response to a second state of the stored semaphore signal in the second or fourth flip-flop, and having a second state in response to the first or second write pulse signal, where the first state of the semaphore signal indicates that the shared resource is owned by the first or second computer and the second state of the semaphore signal indicates that the shared resource is not owned by either the first or second computer; an ownership flip-flop coupled to the second and fourth flip-flop for producing the ownership signal, said ownership signal having a first state in response to a second state of the stored semaphore signal in the fourth flip-flop and having a second state in response to the second state of the stored semaphore signal in the second flip-flop, where the first state of the ownership signal indicates that the shared resource is owned by the second computer and the second state of the ownership signal indicates that the shared resource means is owned by the first computer; and said fourth flip-flop further being coupled to the first and second flip-flop for causing the first flip-flop to store the second state of the ownership signal and the second flip-flop to store the first state of the semaphore signal in response to the second state of the stored semaphore signal in the fourth flip-flop.
Claim 12
Dependent Claim
483 words
Semaphore circuitry for a resource shared by first and second computers generating first and second control signals and coupled to first and second clock signals from first and second signal sources, respectively, said semaphore circuitry comprising: first gating circuitry coupled to the first computer and first clock signal source for generating a first read pulse signal or a first write pulse signal in response to the first control signal and first clock signal; a first flip-flop coupled to the first gating circuitry and an ownership signal for storing the ownership signal in response to the first read pulse signal; a second flip-flop coupled to the first gating circuitry and a semaphore signal for storing the semaphore signal in response to the first read pulse signal; second gating circuitry coupled to the second computer and second clock signal source for generating a second read pulse signal or a second write pulse signal in response to the second control signal and second clock signal; delay circuitry coupled to the ownership signal for generating a delayed ownership signal; a third flip-flop coupled to the second gating circuitry and delay circuitry for storing the delayed ownership signal in response to the second read pulse signal; a fourth flip-flop coupled to the second gating circuitry and the semaphore signal for storing the semaphore signal in response to the second read pulse signal; a semaphore flip-flop coupled to the first and second gating circuitry and the second and fourth flip-flops for producing the semaphore signal, said semaphore signal having a first state in response to a second state of the stored semaphore signal in the second or fourth flip-flop, and having a second state in response to the first or second write pulse signal, where the first state of the semaphore signal indicates that the shared resource is owned by the first or second computer and the second state of the semaphore signal indicates that the shared resource is not owned by either the first or second computer; an ownership flip-flop coupled to the second and fourth flip-flop for producing the ownership signal, said ownership signal having a first state in response to a second state of the stored semaphore signal in the fourth flip-flop and having a second state in response to the second state of the stored semaphore signal in the second flip-flop, where the first state of the ownership signal indicates that the shared resource is owned by the second computer and the second state of the ownership signal indicates that the shared resource means is owned by the first computer; and said fourth flip-flop further being coupled to the first and second flip-flop for causing the first flip-flop to store the second state of the ownership signal and the second flip-flop to store the first state of the semaphore signal in response to the second state of the stored semaphore signal in the fourth flip-flop.
Claim 13
Independent Claim
387 words
A method for use in semaphore circuitry for resource means shared by first and second processing means generating first and second control signals and coupled to first and second clock signals from first and second signal sources, respectively, said method comprising the steps of: generating a first read pulse signal or a first write pulse signal in response to the first control signal and first clock signal; storing an ownership signal in first storage means in response to the first read pulse signal; storing a semaphore signal in second storage means in response to the first read pulse signal; generating a second read pulse signal or a second write pulse signal in response to the second control signal and second clock signal; generating a delayed ownership signal; storing the delayed ownership signal in third storage means in response to the second read pulse signal; storing the semaphore signal in fourth storage means in response to the second read pulse signal; producing a first state of the semaphore signal in response to a second state of the stored semaphore signal in the second or fourth storage means, and a second state of the semaphore signal in response to the first or second write pulse signal, where the first state of the semaphore signal indicates that the shared resource means is owned by the first or second processing means and the second state of the semaphore signal indicates that the shared resource means is not owned by either the first or second processing means; producing a first state of the ownership signal in response to a second state of the stored semaphore signal in the fourth storage means and a second state of the ownership signal in response to the second state of the stored semaphore signal in the second storage means, where the first state of the ownership signal indicates that the shared resource means is owned by the second processing means and the second state of the ownership signal indicates that the shared resource means is owned by the first processing means; and causing the first storage means to store the second state of the ownership signal and the second storage means to store the first state of the semaphore signal in response to the second state of the stored semaphore signal in the fourth storage means.
Claim 14
Independent Claim
387 words
A method for use in semaphore circuitry for resource means shared by first and second processing means generating first and second control signals and coupled to first and second clock signals from first and second signal sources, respectively, said method comprising the steps of: generating a first read pulse signal or a first write pulse signal in response to the first control signal and first clock signal; storing an ownership signal in first storage means in response to the first read pulse signal; storing a semaphore signal in second storage means in response to the first read pulse signal; generating a second read pulse signal or a second write pulse signal in response to the second control signal and second clock signal; generating a delayed ownership signal; storing the delayed ownership signal in third storage means in response to the second read pulse signal; storing the semaphore signal in fourth storage means in response to the second read pulse signal; producing a first state of the semaphore signal in response to a second state of the stored semaphore signal in the second or fourth storage means, and a second state of the semaphore signal in response to the first or second write pulse signal, where the first state of the semaphore signal indicates that the shared resource means is owned by the first or second processing means and the second state of the semaphore signal indicates that the shared resource means is not owned by either the first or second processing means; producing a first state of the ownership signal in response to a second state of the stored semaphore signal in the fourth storage means and a second state of the ownership signal in response to the second state of the stored semaphore signal in the second storage means, where the first state of the ownership signal indicates that the shared resource means is owned by the second processing means and the second state of the ownership signal indicates that the shared resource means is owned by the first processing means; and causing the first storage means to store the second state of the ownership signal and the second storage means to store the first state of the semaphore signal in response to the second state of the stored semaphore signal in the fourth storage means.
References Cited (Backward Citations)
US3919692A
Cited
US4096572A
Cited
US4115851A
Cited
US4145739A
Cited
US4214305A
Cited
US4214304A
Cited
US4344133A
Cited
US4379327A
Cited
US4380798A
Cited
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