US4569048A
Expired / Lapsed
US
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Method and apparatus for memory overlay
Assignee: Genrad Inc
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Filing: 1983-09-19
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Granted: 1986-02-04
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Expires: 2003-09-19
Abstract
Abstract A microprocessor-based system (10) is tested by a testing device (32) that substitutes instructions from a substitute memory (38) for those in the main memory (28) of the system (10) under test. When the processor (12) of the system under test attempts to read a location in its memory (28), it places signals on bus address lines (22) to designate the memory location and places a data-direction signal on a control line (50) to indicate that the memory (28) is to transmit rather than receive information. In ordinary operation, the memory then places its data on bus data lines (24). In order to replace the data from the main memory (28) with data from the substitute memory (38), the testing device (32) senses whether the address lines (22) carry the address of a memory location whose contents are to be substituted. When such an address is detected, it overdrives the control line (50) to cause it to indicate a write rather than a read. This prevents the main memory (28) from placing its data on the data lines (24). Instead, the test device (32) causes its substitute memory (38) to place its contents on the data lines (24). Since there is no contention between the substitute memory (38) and the main memory (28), the contents of the substitute memory (38) can be placed on the data lines (24) without overdriving them.
Inventors
- 👤 Brian Sargent
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:02
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F11/2205; G06F11/2236
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
382 words
In a tester for testing a processor-based system that includes a processor having a processor bus, the processor placing address signals on the bus to designate addresses in its address space and command signals on the bus to direct that data be written into or read from the address-space addresses, the processor-based system also including processor-controlled devices, each of which occupies an address in the processor address space, at least a readable one of the processor-controlled devices being connected to place data on the processor bus in response to the presence on the bus of address signals designating its address and command signals directing that data are to be read from the address-space address, an instruction-substitution system for replacing data from the readable processor-controlled device with substitute data in order to cause the processor to execute test steps rather than steps designated by the data from the readable processor-controlled device, the instruction-substitution system comprising: A. a substitute memory including at least one memory location occupying an address in the processor address space that is also occupied by the readable processor-controlled device, the substitute memory being connectable to the processor bus to place address signals thereon and being operable by application of read signals thereto to place on the processor bus, in response to the presence on the bus of signals designating a substitute-memory location, the contents of the substitute-memory location designated by the address signals on the processor bus; and B. an address-recognition circuit connectable to the processor bus for sensing the address signals thereon and determining whether the address signals designate a substitute-memory location, the address-recognition circuit being connected to the processor bus and the substitute memory to send read signals to the substitute memory and to overcome command signals from the processor so that a processor-controlled device does not receive command signals directing that data be read from it if the processor attempts to place command and address signals on the bus directing that data be read from a location whose address is also occupied by a substitute-memory location, the instruction-substitution system thereby causing the processor to read data from the substitute memory rather than from a processor-controlled device when it attempts to read from a location in the processor-controlled device having an address also occupied by a substitute-memory location.
Claim 2
Dependent Claim
382 words
In a tester for testing a processor-based system that includes a processor having a processor bus, the processor placing address signals on the bus to designate addresses in its address space and command signals on the bus to direct that data be written into or read from the address-space addresses, the processor-based system also including processor-controlled devices, each of which occupies an address in the processor address space, at least a readable one of the processor-controlled devices being connected to place data on the processor bus in response to the presence on the bus of address signals designating its address and command signals directing that data are to be read from the address-space address, an instruction-substitution system for replacing data from the readable processor-controlled device with substitute data in order to cause the processor to execute test steps rather than steps designated by the data from the readable processor-controlled device, the instruction-substitution system comprising: A. a substitute memory including at least one memory location occupying an address in the processor address space that is also occupied by the readable processor-controlled device, the substitute memory being connectable to the processor bus to place address signals thereon and being operable by application of read signals thereto to place on the processor bus, in response to the presence on the bus of signals designating a substitute-memory location, the contents of the substitute-memory location designated by the address signals on the processor bus; and B. an address-recognition circuit connectable to the processor bus for sensing the address signals thereon and determining whether the address signals designate a substitute-memory location, the address-recognition circuit being connected to the processor bus and the substitute memory to send read signals to the substitute memory and to overcome command signals from the processor so that a processor-controlled device does not receive command signals directing that data be read from it if the processor attempts to place command and address signals on the bus directing that data be read from a location whose address is also occupied by a substitute-memory location, the instruction-substitution system thereby causing the processor to read data from the substitute memory rather than from a processor-controlled device when it attempts to read from a location in the processor-controlled device having an address also occupied by a substitute-memory location.
Claim 3
Dependent Claim
68 words
An instruction-substitution system as defined in claim 1 wherein: A. the address-recognition circuit senses whether the processor is attempting to place command signals on the bus directing that data be read from the processor-controlled device; and B. the address-recognition circuit sends read signals to the substitute memory only if the processor attempts to place command signals on the bus directing that data be read from the processor-controlled device.
Claim 4
Dependent Claim
146 words
An instruction-substitution system as defined in claim 2 wherein: A. the processor directs that data be read by sending as a command signal a first voltage within a read voltage region that indicates that the data are to be placed on the bus by the processor-controlled device; B. the processor indicates that data are to be written by sending as a command signal a second voltage within a write voltage region that indicates that data on the bus are to be read by the processor-controlled device; and C. the address-recognition circuit detects an attempt to read data from a processor-controlled device by sensing a control signal between the first voltage and the second voltage but within the write voltage region and, in response, drives the bus to cause the command signal to remain in the write voltage region when the address signals designate a substitute-memory location.
Claim 5
Dependent Claim
284 words
In testing a processor-based system that includes a processor having a processor bus, the processor placing address signals on the bus to designate addresses in its address space and command signals on the bus to direct that data be written into or read from the address-space addresses, the processor-based system also including processor-controlled devices, each of which occupies an address in the processor address space, at least a readable one of the processor-controlled devices being connected to place data on the processor bus in response to the presence on the bus of address signals designating its address and command signals directing that data be read, a method of replacing data from the readable processor-controlled device with substituting data in order to cause the processor to execute test steps rather than steps designated by the data from the readable processor-controlled device, the method comprising the steps of: A. sensing address signals on the bus to determine whether the address signals designate a predetermined address for which instruction substitution is intended; B. if the address signals designate a predetermined address for which instruction substitution is intended and the processor attempts to place command signals on the bus directing that data be read, driving the bus to overcome command signals from the processor so that a processor-controlled device does not receive command signals directing that data be read from it; and C. placing substitute data signals on the bus if the address signals designate a predetermined address for which instruction substitution is intended and the processor attempts to place command signals on the bus that direct that data be read, thereby causing the processor to read the substitute data signals rather than signals from a processor-controlled device.
Claim 6
Dependent Claim
284 words
In testing a processor-based system that includes a processor having a processor bus, the processor placing address signals on the bus to designate addresses in its address space and command signals on the bus to direct that data be written into or read from the address-space addresses, the processor-based system also including processor-controlled devices, each of which occupies an address in the processor address space, at least a readable one of the processor-controlled devices being connected to place data on the processor bus in response to the presence on the bus of address signals designating its address and command signals directing that data be read, a method of replacing data from the readable processor-controlled device with substituting data in order to cause the processor to execute test steps rather than steps designated by the data from the readable processor-controlled device, the method comprising the steps of: A. sensing address signals on the bus to determine whether the address signals designate a predetermined address for which instruction substitution is intended; B. if the address signals designate a predetermined address for which instruction substitution is intended and the processor attempts to place command signals on the bus directing that data be read, driving the bus to overcome command signals from the processor so that a processor-controlled device does not receive command signals directing that data be read from it; and C. placing substitute data signals on the bus if the address signals designate a predetermined address for which instruction substitution is intended and the processor attempts to place command signals on the bus that direct that data be read, thereby causing the processor to read the substitute data signals rather than signals from a processor-controlled device.
Claim 7
Dependent Claim
75 words
A method as recited in claim 4 wherein: A. the method further includes the step of sensing whether the processor is attempting to place command signals on the bus that directs that data be read; and B. the step of placing substitute data signals on the bus is performed only if it is determined in the sensing step the processor is attempting to place command signals on the bus that direct that data be read.
Claim 8
Dependent Claim
172 words
In testing a system that includes a control circuit, a controlled device, and a bus connecting the control circuit to the controlled device for transmission of command signals from the control circuit to the controlled device and data signals from the controlled device to the control circuit, the control circuit sending command signals to the controlled device and the controlled device responding to the command signals to send data signals over the bus to the control circuit, a method of replacing data from the controlled device with substitute data, the method comprising the steps of: A. detecting attempts by the control circuit to command the controlled device to place data signals on the bus; and B. responding to at least some such attempts by: (i) overdriving the bus to prevent command signals that cause the controlled device to place data signals on the bus, thereby preventing the controlled device from placing data signals on the bus; and (ii) placing data signals on the bus in place of signals from the controlled device.
Claim 9
Dependent Claim
172 words
In testing a system that includes a control circuit, a controlled device, and a bus connecting the control circuit to the controlled device for transmission of command signals from the control circuit to the controlled device and data signals from the controlled device to the control circuit, the control circuit sending command signals to the controlled device and the controlled device responding to the command signals to send data signals over the bus to the control circuit, a method of replacing data from the controlled device with substitute data, the method comprising the steps of: A. detecting attempts by the control circuit to command the controlled device to place data signals on the bus; and B. responding to at least some such attempts by: (i) overdriving the bus to prevent command signals that cause the controlled device to place data signals on the bus, thereby preventing the controlled device from placing data signals on the bus; and (ii) placing data signals on the bus in place of signals from the controlled device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-03 | 1989-08-05 | 1990-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-03 | 1993-08-05 | 1994-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-03 | 1997-08-05 | 1998-02-04 | $7700.00 | Window Closed / Lapsed |