Instruction substitution mechanism in an instruction handling unit of a data processing system

Claim 2

An instruction handling unit in a data processing system including a central processor instruction buffer for storing a plurality of program instructions, an execution unit for receiving instructions in sequence from the instruction handling unit for execution by the execution unit, and an addressable main storage system for storing data and instructions, the improvement comprising: instruction sequence detector means, connected to the instruction buffer, including examining means for fields of each of n sequential instructions in the instruction buffer; signalling means, connected and responsive to said examining means, for providing an output signal indicating a sequence of predetermined instructions in said n sequential instructions; and substitute instruction generator means, connected and responsive to said output signal of said signalling means for effecting transfer of a substitute instruction to the execution unit in place of said sequence of n predetermined instructions.

Claim 3

An instruction handling unit in accordance with claim 1 wherein: n=2.

Claim 4

An instruction handling unit in accordance with claim 2 wherein said examining means includes: means connected to the Op-code field of two adjacent instructions in the instruction buffer.

Claim 5

An instruction handling unit in accordance with claim 3 wherein instructions stored in the instruction buffer include, in addition to an Op-code field, general register addressing fields, and a main storage addressing field, and wherein said examining means further includes: means connected to general register addressing fields of two adjacent instructions in the instruction buffer.

Claim 6

An instruction handling unit in accordance with claim 4 wherein: said examining means includes; load recognition means, connected to the Op-code field of the first of said two adjacent instructions, for indicating an instruction effective to transfer data from an addressed main storage location to a specified one of the general registers; equality recognition means, connected and responsive to the general register addressing field of said first instruction, identifying said specified one of the general registers, and connected and responsive to at least one general register addressing field of the second of said two adjacent instructions for providing an equality signal indicating a two-instruction sequence in which said specified one of the general registers is loaded with data from an addressable main storage address by said first instruction, and is utilized during execution of said second instruction; and Op-code identifying means, connected and responsive to the Op-code field of said second instruction to provide one of a plurality of Op-code identifying signals; said signalling means includes; means connected and responsive to said load recognition means, said equality recognition means, and said Op-code identifying means, for providing one of a plurality of output signals associated with one of a plurality of predetermined sequences of said first and said second instructions; and said substitute instruction generator means includes; means, responsive to each of said plurality of output signals from said signalling means, for effecting transfer of a unique substitute instruction for each of said plurality of predetermined sequences of said first and said second instructions as a substitute for said first instruction.

Claim 7

An instruction handling unit in accordance with claim 5 wherein one of said unique substitute instructions includes: a pseudo Op-code field coded to enable execution control means in the execution unit for initiating a first and second access to the main storage system using first and second main storage addresses, said first main storage address specified by said first instruction, and said second main storage address being specified by the data accessed by said first main storage address.