Data processing system having shared memory

Claim 1

In a data processing system having a processor with a memory, a plurality of functional devices initialized by said processor, a buffer memory shared by all of said functional devices for buffering data transfered between said functional devices, shared memory access means for controlling writing from a selected functional device into said shared buffer memory and reading from said shared buffer memory into another selected functional device, wherein said shared memory access means includes a pointer table having a plurality of entries each capable of retaining an address for said shared buffer memory and wherein said processor initializes, in response to a data transfer request from a functional device, said pointer table, and first and second functional devices active in said data transfer, the improvement comprising: said functional devices having means for generating one or more control codes representing access status for said shared buffer memory; said control codes include a first code representing that said buffer memory is available for writing and a second code representing that said shared buffer memory is available for reading; and said active functional devices, after being initialized by said processor, transferring data between each other through said shared buffer memory under control of said shared memory access means and independent of said processor by interchanging said control codes with each other, said first active device enabling said shared memory access means to control the transfer of data from said first active device to said buffer memory when said first code is received from said second active device, said second active device enabling said shared memory access means to control the transfer of data from said buffer memory to said second active device when said second code is received from said first active device.