Multi-processor system with programmable memory-access priority control

Claim 2

A multi-processor system comprising: a plurality of processors; a common shared memory for use by said processors, said processors each adapted to generate a respective memory request signal to request access to said common shared memory; a bus connected to said processors and said memory for transferring data from said processors to said memory or from said memory to said processors; register means for storing priority information designating a memory access grade priority for each of said processors, said priority information changeable in a predetermined manner and remaining fixed irrespective of access of said memory by any of said processors until being changed in said predetermined manner, said register means outputting priority information signals which indicate the memory access grade priority of each of said processors; and priority control means for receiving said priority information signals from said register means, for receiving said memory request signals from said processors when said processors request access of said memory, and for outputting an acknowledge signal enabling memory access to that processor requesting use of the memory and having among the processors requesting memory access the highest memory access grade priority stored in said register means; whereby the priority of memory access of said processors is changed by changing the contents of said register means.

Claim 3

A multi-processor system according to claim 1, wherein said plurality of processors include: a central processing unit, and a direct memory access channel controller.

Claim 4

A multi-processor system according to claim 1, wherein said register means includes: a flip-flop register.

Claim 5

A multi-processor system according to claim 1, wherein said register means includes: at least one flip-flop for each of said processors.

Claim 6

A multi-processor system according to claim 1, wherein said priority control means comprises: a memory request detecting circuit for receiving said priority information signals from said register means, for receiving said memory request signals from said processors when said processors request memory access of said memory, and for outputting memory request detecting signals which indicate whether each memory access grade priority is being requested or not; a grade priority selecting circuit for receiving said memory request detecting signals from said memory request detecting circuit and for outputting grade priority select detecting signals which indicate the highest grade priority among said grade priorities being requested; a selected grade priority--corresponding processor converting circuit for receiving said grade priority select detecting signals from said grade priority selecting circuit, for receiving said priority information signals from said register means, and for outputting processor indicating signals which indicate a selected processor corresponding to said highest grade priority; and an acknowledge signal generating circuit for receiving said processor indicating signals and for outputting said acknowledge signal to said selected processor.

Claim 7

A multi-processor system comprising: a plurality of processors; a common shared memory for use by said processors, said processors each adapted to generate a respective memory request signal to request access to said common shared memory; a bus connected to said processors and said memory for transferring data from said processors to said memory or from said memory to said processors; first register means for storing first priority information designating a first memory access grade priority for each of said processors, said first priority information changeable in a predetermined manner and remaining fixed irrespective of access of said memory by any of said processors until being changed in said predetermined manners, said first register means outputting first priority information signals which indicate the first memory access grade priority of each of said processors; second register means for storing inhibit information which can be changed, and for outputting inhibit information signals which inhibit selected ones of said processors from using the common shared memory; gate means for receiving said first priority information signals from said first register means, for receiving said inhibit information signals from said second register means, and for outputting second priority information signals which indicate a second memory access grade priority of each of said processors with the selected ones of said processors inhibited by said second register means; and a priority control means for receiving said second priority information signals from said gate means, for receiving said memory request signals from said processors when said processors request memory access of said memory, and for outputting an acknowledge signal enabling memory access to that processor requesting use of the memory and having among the processors requesting memory access the highest second memory access grade priority in accordance with the condition of said second priority information signals outputted by said gate means.

Claim 8

A multi-processor system comprising: a plurality of processors; a common shared memory for use by said processors, said processors each adapted to generate a respective memory request signal to request access to said common shared memory; a bus connected to said processors and said memory for transferring data from said processors to said memory or from said memory to said processors; first register means for storing first priority information designating a first memory access grade priority for each of said processors, said first priority information changeable in a predetermined manner and remaining fixed irrespective of access of said memory by any of said processors until being changed in said predetermined manners, said first register means outputting first priority information signals which indicate the first memory access grade priority of each of said processors; second register means for storing inhibit information which can be changed, and for outputting inhibit information signals which inhibit selected ones of said processors from using the common shared memory; gate means for receiving said first priority information signals from said first register means, for receiving said inhibit information signals from said second register means, and for outputting second priority information signals which indicate a second memory access grade priority of each of said processors with the selected ones of said processors inhibited by said second register means; and a priority control means for receiving said second priority information signals from said gate means, for receiving said memory request signals from said processors when said processors request memory access of said memory, and for outputting an acknowledge signal enabling memory access to that processor requesting use of the memory and having among the processors requesting memory access the highest second memory access grade priority in accordance with the condition of said second priority information signals outputted by said gate means.

Claim 9

A multi-processor system according to claim 6, wherein said plurality of processors include: a central processing unit, and a direct memory access channel controller.

Claim 10

A multi-processor system according to claim 6, wherein said first register means includes a plurality of flip-flop registers, and said second register means includes at least one flip-flop register.

Claim 11

A multi-processor system according to claim 6, wherein said priority control means comprises: a memory request detecting circuit for receiving said second priority information signals from said gate means, for receiving said memory request signals from said processors when said processors request memory access of said memory, and for outputting memory request detecting signals which indicate whether or not each grade priority is being requested; a grade priority selecting circuit for receiving said memory request detecting signals from said memory request detecting circuit and for outputting grade priority select detecting signals which indicate the highest grade priority among said second grade priorities of said processors requesting memory access; a selected grade priority--corresponding processor converting circuit for receiving said grade priority select detecting signals from said grade priority selecting circuit, for receiving said second priority information signals from said gate means, and for outputting processor indicating signals which indicate a selected processor corresponding to said highest second grade priority of said processors requesting memory access; and an acknowledge signal generating circuit for receiving said processor indicating signals, and for outputting said acknowledge signal to said processor selected by said selected grade priority corresponding processor converting circuit.