US4488217A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing system with lock-unlock instruction facility
Assignee: Compaq Information Technologies Group LP
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Filing: 1981-05-19
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Granted: 1984-12-11
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Expires: 2001-05-19
Abstract
Abstract A data processing system including a plurality of data units and a common bus. The data unit includes apparatus for issuing instructions including a LOCK instruction and an UNLOCK instruction. Each data unit includes apparatus responsive to the instructions such that, if the first data unit issues a LOCK instruction, the data unit other than the first data unit, are prevented from transferring information over the common bus with a LOCK instruction until an UNLOCK instruction is issued by any data unit.
Inventors
- 👤 Paul Binder
- 👤 David A. Cane
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:22
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/14; G06F13/36; G06F13/368; G06F13/374
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
298 words
A data processing system including a memory, a first and second data means, and a common bus interconnecting said memory and said first and second data means for transferring data and data transfer instruction signals which enable the transfer of data between said memory and said first and second data means over said common bus, said data transfer instruction signals including signals representing a first instruction and signals representing a second instruction, each of said first and second data means including: (i) data transfer instruction signal transmitting means connected to said data transfer instruction signal transfer means for transmitting data transfer instruction signals including signals representing the first instruction and signals representing the second instruction; (ii) inhibit signal transmitting means for transmitting an inhibit signal to said data transfer instruction signal transmitting means to inhibit it from transmitting a first instruction; (iii) decoding means connected to said data transfer instruction signal transfer means and said inhibit signal transmitting means for decoding the data transfer instruction signals and for enabling said inhibit signal transmitting means to transmit said inhibit signal in response to the receipt of said first instruction from said data transfer instruction signal transfer means; (iv) first disabling means connected to its respective data transfer instruction signal transmitting means and said decoding means for disabling the respective decoding means when the connected data transfer instruction signal transmitting means transmits the first instruction; and (v) second disabling means connected to its respective inhibiting signal transmitting means and said data transfer instruction signal transfer means and responsive to the receipt of signals representing the second instruction from said data transfer instruction signal transfer means for disabling said inhibiting signal transmitting means to thereafter enable its respective data transfer instruction signal transmitting means to transmit signals representing the first instruction.
Claim 2
Dependent Claim
298 words
A data processing system including a memory, a first and second data means, and a common bus interconnecting said memory and said first and second data means for transferring data and data transfer instruction signals which enable the transfer of data between said memory and said first and second data means over said common bus, said data transfer instruction signals including signals representing a first instruction and signals representing a second instruction, each of said first and second data means including: (i) data transfer instruction signal transmitting means connected to said data transfer instruction signal transfer means for transmitting data transfer instruction signals including signals representing the first instruction and signals representing the second instruction; (ii) inhibit signal transmitting means for transmitting an inhibit signal to said data transfer instruction signal transmitting means to inhibit it from transmitting a first instruction; (iii) decoding means connected to said data transfer instruction signal transfer means and said inhibit signal transmitting means for decoding the data transfer instruction signals and for enabling said inhibit signal transmitting means to transmit said inhibit signal in response to the receipt of said first instruction from said data transfer instruction signal transfer means; (iv) first disabling means connected to its respective data transfer instruction signal transmitting means and said decoding means for disabling the respective decoding means when the connected data transfer instruction signal transmitting means transmits the first instruction; and (v) second disabling means connected to its respective inhibiting signal transmitting means and said data transfer instruction signal transfer means and responsive to the receipt of signals representing the second instruction from said data transfer instruction signal transfer means for disabling said inhibiting signal transmitting means to thereafter enable its respective data transfer instruction signal transmitting means to transmit signals representing the first instruction.
Claim 3
Dependent Claim
79 words
A data processing system as defined in claim 1 wherein each said first and second data means second disabling means includes a second decoding means connected to said data transfer instruction signal transfer means and to said inhibiting signal transmitting means, each said second decoding means being responsive to the second instruction for inhibiting said inhibiting signal transmitting means from transmitting said inhibiting signal to permit said data transfer instruction signal transmitting means to thereafter transmit the first instruction.
Claim 4
Dependent Claim
273 words
A data means for connection to a data processing system including a common bus including a memory, and means for transferring data and data transfer instruction signals which enable the transfer of data between said data means and the memory, said data transfer instruction signals representing a first instruction and signals representing a second instruction, said data means including: (i) data transfer instruction signal transmitting means connected to said data transfer instruction signal transfer means for transmitting data transfer instruction signals including signals representing the first instruction and signals representing the second instruction; (ii) inhibit signal transmitting means for transmitting an inhibit signal to said data transfer instruction signal transmitting means to inhibit it from transmitting a first instruction; (iii) decoding means connected to said data transfer instruction signal transfer means and said inhibit signal transmitting means for decoding the data transfer instruction signals and for enabling said inhibit signal transmitting means to transmit said inhibit signal in response to the receipt of said first instruction from said data transfer instruction signal transfer means; (iv) first disabling means connected to said data transfer instruction signal transmitting means and said decoding means for disabling said decoding means when the connected data transfer instruction signal transmitting means transmits the first instruction; and (v) second disabling means connected to said inhibiting signal transmitting means and said data transfer instruction signal transfer means and responsive to the receipt of signals representing the second instruction from said data transfer instruction signal transfer means for disabling said inhibiting signal transmitting means to thereafter enable its respective data transfer instruction signal transmitting means to transmit signals representing the first instruction.
Claim 5
Dependent Claim
273 words
A data means for connection to a data processing system including a common bus including a memory, and means for transferring data and data transfer instruction signals which enable the transfer of data between said data means and the memory, said data transfer instruction signals representing a first instruction and signals representing a second instruction, said data means including: (i) data transfer instruction signal transmitting means connected to said data transfer instruction signal transfer means for transmitting data transfer instruction signals including signals representing the first instruction and signals representing the second instruction; (ii) inhibit signal transmitting means for transmitting an inhibit signal to said data transfer instruction signal transmitting means to inhibit it from transmitting a first instruction; (iii) decoding means connected to said data transfer instruction signal transfer means and said inhibit signal transmitting means for decoding the data transfer instruction signals and for enabling said inhibit signal transmitting means to transmit said inhibit signal in response to the receipt of said first instruction from said data transfer instruction signal transfer means; (iv) first disabling means connected to said data transfer instruction signal transmitting means and said decoding means for disabling said decoding means when the connected data transfer instruction signal transmitting means transmits the first instruction; and (v) second disabling means connected to said inhibiting signal transmitting means and said data transfer instruction signal transfer means and responsive to the receipt of signals representing the second instruction from said data transfer instruction signal transfer means for disabling said inhibiting signal transmitting means to thereafter enable its respective data transfer instruction signal transmitting means to transmit signals representing the first instruction.
Claim 6
Dependent Claim
71 words
A data means as defined in claim 3 wherein second disabling means includes a second decoding means connected to said data transfer instruction signal transfer means and to said inhibiting signal transmitting means, each said second decoding means being responsive to the second instruction for inhibiting said inhibiting signal transmitting means from transmitting said inhibiting signal to permit said data transfer instruction signal transmitting means to thereafter transmit the first instruction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-11 | 1988-06-11 | 1988-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-11 | 1992-06-11 | 1992-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-11 | 1996-06-11 | 1996-12-11 | $7700.00 | Window Closed / Lapsed |