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US4426768A Expired / Lapsed US ⏱️ 0.0 years remaining

Ultra-thin microelectronic pressure sensors

Assignee: RTX Corp
•
Filing: 1981-12-28
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Granted: 1984-01-24
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Expires: 2001-12-28
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Abstract

Abstract A plurality of thin pressure sensors are made by processing a first large wafer (20, 110) to provide a plurality of electronic devices (28, 122, 124, 125) having a characteristic which varies inversely with strain, and processing a second wafer (40) to provide a plurality of cavities (46) each registered on the second wafer so as to be registerable with a corresponding device on the first wafer. The wafers (20, 40, 110) have thick undoped silicon substrates (21, 41, 114) which are utilized as handles or carriers during the processing, and are stripped off by etching to a highly doped boron etch stop layer (22, 42, 112) when the processing has proceeded to a point where the need therefore has been satisfied. The first wafers (20, 110) are provided with a suitable pattern of borosilicate glass (except in the region where the pressure sensors are formed) so that the two wafers may be joined by a field assisted bonding at a suitable temperature in a vacuum. Electric contact to the devices is provided by holes (51, FIG. 9; 56-59, FIG. 13) through the entire wafer.

Inventors

  • 👤 James F. Black
  • 👤 Thomas W. Grudkowski
  • 👤 Anthony J. DeMaria

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 16:18
CPC Classifications
B; B81; B81C; B81C1/00; B81C1/00015; B81C1/00261; B81C1/00333; G; G01; G01L; G01L9/00; G01L9/0041; G01L9/0042; G01L9/0051; G01L9/0052; G01L9/0054; G01B; G01B2210/00; G01B2210/64

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 355 words
A method of forming a plurality of ultra-thin microelectronic pressure sensors comprising: processing a first wafer having a first thick undoped silicon substrate extending from a first surface of said first wafer and a first highly doped silicon etch stop layer adjacent to said substrate to provide a plurality of devices at a second surface of said first wafer, each of which provides an electrical characteristic which varies with strain at said second surface; providing a layer of borosilicate glass over the entire second surface of said first wafer except in the regions where said devices are formed; processing a second wafer having a second thick undoped silicon substrate extending from a first surface of said second wafer and a second highly doped silicon etch stop layer adjacent to said substrate to provide a plurality of cavities in said second wafer extending from a second surface of said second wafer, each of said cavities disposed on said second wafer so that, with said first and second wafers properly registered with their second surfaces adjacent one another, each of said devices will be disposed adjacent to a corresponding one of said cavities; contacting the borosilicate glass layer of said first wafer with said second surface of said second wafer, with said wafers registered so that each of said cavities is adjacent to a corresponding one of said devices; joining said wafers by field assisted bonding in a vacuum to provide a composite wafer including a plurality of absolute pressure sensors, each formed by a corresponding set of a device and a cavity; stripping said second undoped silicon substrate from said composite wafer by etching from said first surface of said second wafer to said second etch stop layer; cutting said composite wafer into a plurality of chips, each having one of said pressure sensors; bonding each of said chips to a metallic carrier; stripping said first undoped silicon substrate from each of said chips by etching from said first surface of said first wafer to said first etch stop layer; and providing conductors on each of said chips to make electrical contact with the devices thereon.
Claim 2
Independent Claim 355 words
A method of forming a plurality of ultra-thin microelectronic pressure sensors comprising: processing a first wafer having a first thick undoped silicon substrate extending from a first surface of said first wafer and a first highly doped silicon etch stop layer adjacent to said substrate to provide a plurality of devices at a second surface of said first wafer, each of which provides an electrical characteristic which varies with strain at said second surface; providing a layer of borosilicate glass over the entire second surface of said first wafer except in the regions where said devices are formed; processing a second wafer having a second thick undoped silicon substrate extending from a first surface of said second wafer and a second highly doped silicon etch stop layer adjacent to said substrate to provide a plurality of cavities in said second wafer extending from a second surface of said second wafer, each of said cavities disposed on said second wafer so that, with said first and second wafers properly registered with their second surfaces adjacent one another, each of said devices will be disposed adjacent to a corresponding one of said cavities; contacting the borosilicate glass layer of said first wafer with said second surface of said second wafer, with said wafers registered so that each of said cavities is adjacent to a corresponding one of said devices; joining said wafers by field assisted bonding in a vacuum to provide a composite wafer including a plurality of absolute pressure sensors, each formed by a corresponding set of a device and a cavity; stripping said second undoped silicon substrate from said composite wafer by etching from said first surface of said second wafer to said second etch stop layer; cutting said composite wafer into a plurality of chips, each having one of said pressure sensors; bonding each of said chips to a metallic carrier; stripping said first undoped silicon substrate from each of said chips by etching from said first surface of said first wafer to said first etch stop layer; and providing conductors on each of said chips to make electrical contact with the devices thereon.
Claim 3
Independent Claim 295 words
A method of forming a plurality of ultra-thin, composite microelectronic devices comprising: processing a first wafer having a thick undoped silicon substrate extending from a first surface of said first wafer and a highly doped silicon etch stop layer adjacent to said substrate to provide a plurality of electronic devices at a second surface of said first wafer; providing a layer of borosilicate glass over the entire second surface of said first wafer except in the regions where said devices are formed; processing a second wafer to provide a plurality of cavities in said second wafer extending from a second surface of said second wafer, each of said cavities disposed on said second wafer so that, with said first and second wafers properly registered with their second surfaces adjacent one another, each of said devices will be disposed adjacent to a corresponding one of said cavities; contacting the borosilicate glass layer of said first wafer with said second surface of said second wafer, with said wafers registered so that each of said cavities is adjacent to a corresponding one of said devices; joining said wafers by field assisted bonding in a vacuum to provide a composite wafer including a plurality of said devices each formed on a surface adjacent a corresponding cavity; cutting said composite wafers into a plurality of chips, each having one of said devices; stripping said first undoped silicon substrate from each of said chips by etching from said first surface to said etch stop layer; etching through said chips from the surface of said etch stop layer which became exposed by stripping of said substrate to the electronic device on said chip, thereby to form access holes; and attaching electrical conductors to the devices on said chips through said access holes.
Claim 4
Independent Claim 295 words
A method of forming a plurality of ultra-thin, composite microelectronic devices comprising: processing a first wafer having a thick undoped silicon substrate extending from a first surface of said first wafer and a highly doped silicon etch stop layer adjacent to said substrate to provide a plurality of electronic devices at a second surface of said first wafer; providing a layer of borosilicate glass over the entire second surface of said first wafer except in the regions where said devices are formed; processing a second wafer to provide a plurality of cavities in said second wafer extending from a second surface of said second wafer, each of said cavities disposed on said second wafer so that, with said first and second wafers properly registered with their second surfaces adjacent one another, each of said devices will be disposed adjacent to a corresponding one of said cavities; contacting the borosilicate glass layer of said first wafer with said second surface of said second wafer, with said wafers registered so that each of said cavities is adjacent to a corresponding one of said devices; joining said wafers by field assisted bonding in a vacuum to provide a composite wafer including a plurality of said devices each formed on a surface adjacent a corresponding cavity; cutting said composite wafers into a plurality of chips, each having one of said devices; stripping said first undoped silicon substrate from each of said chips by etching from said first surface to said etch stop layer; etching through said chips from the surface of said etch stop layer which became exposed by stripping of said substrate to the electronic device on said chip, thereby to form access holes; and attaching electrical conductors to the devices on said chips through said access holes.

References Cited (Backward Citations)

US4103273A Cited
US4121334A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-01-23 1987-07-25 1988-01-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-01-23 1991-07-25 1992-01-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-01-23 1995-07-25 1996-01-24 $7700.00 Window Closed / Lapsed

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