Digital sequence detector

Claim 1

A digital sequence detector for detecting a predetermined serial sequence of L bits and comprising: a shift register having N stages for serially receiving said serial sequence of L bits with the reception of each additional bit constituting a new group of N bits contained in said shift register; memory means having X memory locations, N+M input terminals, and at least M output terminals; first means for supplying the contents of said N stages of said shift register to said N input terminals of said memory means; second means for supplying the signals on said M output terminals of said memory means to the M input terminals of said memory means; said second means comprising means for delaying the supplying of the signals appearing on the M output terminals of said memory means to the M input terminals thereof until the next bit of said expected sequence has been entered into said shift register means to form a next successive group of N signals; said memory means responsive to each next successive group of N signals supplied thereto from said shift register and the delayed signals on the M output terminals of said memory means to produce a predetermined sequence of binary patterns on said M output terminals thereof as long as the predetermined sequence of L bits is being correctly received into said shift register; and means responsive to the last predetermined binary pattern supplied from said memory means to indicate the reception of the complete sequence of L binary bits received by said shift register; said memory means being responsive to any group of N bits in said shift register which varies from any expected group of N bits to output the first binary pattern in said sequence of binary patterns.

Claim 3

A system for detecting an input signal comprising a predetermined serial sequence of L bits and comprising: N terminals; addressable memory means having N+M input terminals and M output terminals and responsive to encoded addressing signals supplied to said N+M input terminals to supply the contents of the addressed memory location to said M output terminals; and a shift register for supplying successive N bit segments of said received serial sequence of L bits to said N input terminals every Wth received bit, where W<L, and the contents of the addressed memory location of said memory means which appears on said M output terminals to said M input terminals; said memory means responsive to the signals appearing on said N+M input terminals to address successive memory locations in said memory means whose contents form a predetermined sequence of binary patterns as long as the L bits of the received input signal are correctly received in said serial sequence; said memory means further responsive to a deviation of the received input signal from said predetermined serial sequence to supply a selected one of said binary patterns other than the next sequential binary pattern in said predetermined sequence of binary patterns to said M output terminals.

Claim 4

A system for detecting an input signal comprising a predetermined serial sequence of L bits and comprising: N terminals; addressable memory means having N+M input terminals and M output terminals and responsive to encoded addressing signals supplied to said N+M input terminals to supply the contents of the addressed memory location to said M output terminals; and a shift register for supplying successive N bit segments of said received serial sequence of L bits to said N input terminals every Wth received bit, where W<L, and the contents of the addressed memory location of said memory means which appears on said M output terminals to said M input terminals; said memory means responsive to the signals appearing on said N+M input terminals to address successive memory locations in said memory means whose contents form a predetermined sequence of binary patterns as long as the L bits of the received input signal are correctly received in said serial sequence; said memory means further responsive to a deviation of the received input signal from said predetermined serial sequence to supply a selected one of said binary patterns other than the next sequential binary pattern in said predetermined sequence of binary patterns to said M output terminals.

Claim 5

A method for detecting a predetermined expected serial sequence of L bits and comprising the steps of: serially receiving said serial sequence of L bits with the reception of each additional W bits constituting a new group of N received bits, where W is an integer <<N; providing a memory means having X memory locations, N+M input terminals, and at least M output terminals; means for delaying the output binary signal patterns appearing on the M output terminals of said memory means until the next bit of said expected serial sequence has been received to form the next successive group of N signals; supplying each next successive group of N received bits to said N input terminals of said memory means and the delayed signals on said M output terminals of said memory means to the M input terminals of said memory means; producing a predetermined sequence of binary patterns on the M output terminals of said memory means as long as the predetermined sequence of L bits is being received; determining the reception of the complete expected serial sequence of L binary bits by the supplying of a first unique binary pattern from said memory means; and determining a deviation of the sequence of binary patterns from said predetermined sequence of binary patterns by causing said memory means to output a predetermined binary pattern in response to said deviation in preparation of the reception of the next predetermined sequence of binary patterns.

Claim 6

A method for detecting a predetermined expected serial sequence of L bits and comprising the steps of: serially receiving said serial sequence of L bits with the reception of each additional W bits constituting a new group of N received bits, where W is an integer <<N; providing a memory means having X memory locations, N+M input terminals, and at least M output terminals; means for delaying the output binary signal patterns appearing on the M output terminals of said memory means until the next bit of said expected serial sequence has been received to form the next successive group of N signals; supplying each next successive group of N received bits to said N input terminals of said memory means and the delayed signals on said M output terminals of said memory means to the M input terminals of said memory means; producing a predetermined sequence of binary patterns on the M output terminals of said memory means as long as the predetermined sequence of L bits is being received; determining the reception of the complete expected serial sequence of L binary bits by the supplying of a first unique binary pattern from said memory means; and determining a deviation of the sequence of binary patterns from said predetermined sequence of binary patterns by causing said memory means to output a predetermined binary pattern in response to said deviation in preparation of the reception of the next predetermined sequence of binary patterns.