US3942152A
Expired / Lapsed
US
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Verification arrangement
Assignee: Telefonaktiebolaget LM Ericsson AB
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Filing: 1974-11-11
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Granted: 1976-03-02
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Expires: 1994-11-11
Abstract
Abstract A pulse pattern detector includes a local pulse pattern generator starting in response to an incoming signal impulse whether or not it is included in the pulse pattern to be detected. There is a number of timing circuits for measuring the time lapsed from each of the pulses in the locally generated pulse pattern and memory means for storing the measured value of all but the last timing circuit as soon as a signal impulse is received. Comparators are provided to compare the contents of the memory means to find if all the memory circuits have recordings equal to a state of the timing circuit in which case a signal is generated indicating that the desired pulse pattern is detected in the incoming pulse sequence.
Inventors
- 👤 Georg Gustaf Lennart Pettersson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 10:10
CPC Classifications
G; G01; G01S; G01S13/00; G01S13/02; G01S13/06; G01S13/08; G01S13/10; G01S13/30; H; H04; H04L; H04L1/00; H04L1/20
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
173 words
Arrangement for verification that a received sequence of signal pulses includes a certain pulse pattern consisting of N signal pulses distributed in a determined manner in time comprising a code pulse source for local production of said pulse pattern in response to a received signal pulse, a group of N-1 time measuring circuits which are arranged to be started by each one of the N-1 first locally produced pulses and a further time measuring circuit which is arranged to be started by the Nth locally produced pulse, memory means for storing the measuring values from said group of time measuring circuits during an initial part of each incoming signal pulse, and for reading the measuring values thus stored at least during the later part of each signal pulse, and, means for comparing the measuring values thus stored with the measuring values of the further time measuring circuit, and means for emitting a verification signal when the last mentioned time measuring circuit reaches a measuring value which is found in all the memory means.
Claim 2
Dependent Claim
173 words
Arrangement for verification that a received sequence of signal pulses includes a certain pulse pattern consisting of N signal pulses distributed in a determined manner in time comprising a code pulse source for local production of said pulse pattern in response to a received signal pulse, a group of N-1 time measuring circuits which are arranged to be started by each one of the N-1 first locally produced pulses and a further time measuring circuit which is arranged to be started by the Nth locally produced pulse, memory means for storing the measuring values from said group of time measuring circuits during an initial part of each incoming signal pulse, and for reading the measuring values thus stored at least during the later part of each signal pulse, and, means for comparing the measuring values thus stored with the measuring values of the further time measuring circuit, and means for emitting a verification signal when the last mentioned time measuring circuit reaches a measuring value which is found in all the memory means.
Claim 3
Dependent Claim
36 words
Arrangement according to claim 1 wherein the time measuring circuits comprise a clock pulse source and a plurality of counters controlled by said clock pulse source, which also controls the local generation of the pulse pattern.
Claim 4
Dependent Claim
58 words
Arrangement according to claim 2 wherein the memory means include p memory cells each with q bit positions, and the counters are so connected to the memory means that the p most significant positions of the counters give the address to the memory cells while their q least significant positions give the contents in the cells thus addressed.
Claim 5
Dependent Claim
52 words
Arrangement according to claim 3 further comprising selectors for connecting at predetermined times the address inputs of the memory means allotted to the respective counters of said group of N-1 time measuring circuits and for connecting at a later time the address inputs to the counter of said further time measuring circuit.
Claim 6
Dependent Claim
24 words
Arrangement according to claim 1 wherein said memory means stores the measuring value in response to said memory means receipt of a signal pulse.
Claim 7
Dependent Claim
26 words
Arrangement according to claim 5 further including means for delaying the transmission of the signal pulses to said memory means for a predetermined period of time.
Claim 8
Dependent Claim
24 words
Arrangement according to claim 6 further including means for delaying the start of said further time measuring circuit by another predetermined period of time.
References Cited (Backward Citations)
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US3493929A
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US3761891A
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US3691305A
Cited
US3855593A
Cited
US3766316A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-03-02 | 1979-09-01 | 1980-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-03-02 | 1983-09-01 | 1984-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-03-02 | 1987-09-01 | 1988-03-02 | $7700.00 | Window Closed / Lapsed |