Multiprocessor system with high density memory set architecture including partitionable cache store interface to shared disk drive memory

Claim 2

In a multiprocessing system, a partitionable cache store interface to a shared disk drive memory, comprising: a cache storage memory having a data input and output connected to a data bus communicating in common with a plurality of distributed processors and with said disk drive memory, for storing data sets for each of said processors in mutually exclusive partitions; a direct memory access (DMA) controller having a control line connected to each of said processors and to said disk drive memory, for receiving bus allocation demands from said processors and allocating time divided access for selected ones of said processors to said data bus for transferring data to or from corresponding ones of said partitions in said cache storage memory; word counter in said DMA controller having an input connected to a selected processor, for counting the quantity of data stored in the corresponding partition of said cache storage memory and initiating a bus allocation demand for said disk drive memory to obtain time divided access to said data bus for transferring data from said corresponding partition to said disk drive memory; whereby data can be transferred between said plurality of processors and said cache memory and between said cache memory and said disk drive memory on a time divided basis.

Claim 3

The apparatus of claim 1, which further comprises: a plurality of word counters in said DMA controller, each having an input respectively connected to a corresponding one of said processors, for counting the quantity of data stored in each corresponding one of said partitions of said cache storage memory and initiating a bus allocation demand for said disk drive memory to obtain time divided access to said data bus for transferring data from said corresponding partitions to said disk drive memory.

Claim 4

The apparatus of claim 1, wherein data transfers between said cache memory and said processors occurs at a first data rate and data transfers between said cache memory and said disk drive memory occur at a second data rate different from said first data rate.

Claim 5

The apparatus of claim 1, which further comprises: said cache storage memory including a command word partition for the storage of data transfer command words received over said data bus on a time divided basis from said distributed processors; a local control processor having a data line connected to said data input and output of said cache storage memory and a control line connected to said DMA controller, for accessing and decoding said command words from said cache memory; said local control processor signalling said DMA controller in response to one of said decoded command words, to control data transfers between said cache storage memory and said distributed processors or said disk drive memory.

Claim 6

A multiprocessing system including a partitionable cache store interface to a shared disk drive memory, comprising: a plurality of host adapters, each respectively connected between one of a plurality of distributed data processors and a common data bus; a disk adapter connected between said disk drive memory and said common data bus; a cache storage memory having a data input and output connected to said data bus for storing data sets for each of said processors in mutually exclusive partitions; a direct memory access (DMA) controller having a control line connected to each of said host adapters and to said disk adapter, for receiving bus allocation demands from said processors and allocating time divided access for selected ones of said processors to said data bus for transferring data to or from corresponding ones of said partitions in said cache storage memory; a word counter in said DMA controller having an input connected to a selected host adapter, for counting the quantity of data stored in the corresponding partition of said cache storage memory and initiating a bus allocation demand for said disk drive memory to obtain time divided access to said data bus for transferring data from said corresponding partition to said disk drive memory; whereby data can be transferred between said plurality of processors and said cache memory and between said cache memory and said disk drive memory on a time divided basis.

Claim 7

A multiprocessing system including a partitionable cache store interface to a shared disk drive memory, comprising: a plurality of host adapters, each respectively connected between one of a plurality of distributed data processors and a common data bus; a disk adapter connected between said disk drive memory and said common data bus; a cache storage memory having a data input and output connected to said data bus for storing data sets for each of said processors in mutually exclusive partitions; a direct memory access (DMA) controller having a control line connected to each of said host adapters and to said disk adapter, for receiving bus allocation demands from said processors and allocating time divided access for selected ones of said processors to said data bus for transferring data to or from corresponding ones of said partitions in said cache storage memory; a word counter in said DMA controller having an input connected to a selected host adapter, for counting the quantity of data stored in the corresponding partition of said cache storage memory and initiating a bus allocation demand for said disk drive memory to obtain time divided access to said data bus for transferring data from said corresponding partition to said disk drive memory; whereby data can be transferred between said plurality of processors and said cache memory and between said cache memory and said disk drive memory on a time divided basis.

Claim 8

The apparatus of claim 5, which further comprises: a plurality of word counters in said DMA controller, each having an input respectively connected to a corresponding one of said host adapters, for counting the quantity of data stored in each corresponding one of said partitions of said cache storage memory and initiating a bus allocation demand for said disk drive memory to obtain time divided access to said data bus for transferring data from said corresponding partitions to said disk drive memory.

Claim 9

The apparatus of claim 5, wherein data transfers between said cache memory and said host adapters occurs at a first data rate and data transfers between said cache memory and said disk adapter occur at a second data rate different from said first data rate.

Claim 10

The apparatus of claim 5, which further comprises: said cache storage memory including a command word partition for the storage of data transfer command words received over said data bus on a time divided basis from said distributed processors; a local control processor having a data line connected to said data input and output of said cache storage memory and a control line connected to said DMA controller, for accessing and decoding said command words from said cache memory; said local control processor signalling said DMA controller in response to one of said decoded command words, to control data transfers between said cache storage memory and said host adapters or said disk adapter.

Claim 11

In a multiprocessing system, a partitionable cache store interface to a shared disk drive memory, comprising: a cache storage memory having a data input and output connected to a data bus communicating in common with a plurality of distributed processors and with said disk drive memory, for storing data sets for each of said processors in mutually exclusive partitions; a direct memory access (DMA) controller having a control line connected to each of said processors and to said disk drive memory, for receiving bus allocation demands from said processors and allocating time divided access for selected ones of said processors or said disk drive memory to said data bus for transferring data to or from corresponding ones of said partitions in said cache storage memory; said cache storage memory including a command word partition for the storage of data transfer command words received over said data bus on a time divided basis from said distributed processors; a local control processor having a data line connected to said data input and output of said cache storage memory and a control line connected to said DMA controller, for accessing and decoding said command words from said cache memory; said local control processor signalling said DMA controller in response to one of said decoded command words, to control data transfers between said cache storage memory and said distributed processors or said disk drive memory.

Claim 12

In a multiprocessing system, a partitionable cache store interface to a shared disk drive memory, comprising: a cache storage memory having a data input and output connected to a data bus communicating in common with a plurality of distributed processors and with said disk drive memory, for storing data sets for each of said processors in mutually exclusive partitions; a direct memory access (DMA) controller having a control line connected to each of said processors and to said disk drive memory, for receiving bus allocation demands from said processors and allocating time divided access for selected ones of said processors or said disk drive memory to said data bus for transferring data to or from corresponding ones of said partitions in said cache storage memory; said cache storage memory including a command word partition for the storage of data transfer command words received over said data bus on a time divided basis from said distributed processors; a local control processor having a data line connected to said data input and output of said cache storage memory and a control line connected to said DMA controller, for accessing and decoding said command words from said cache memory; said local control processor signalling said DMA controller in response to one of said decoded command words, to control data transfers between said cache storage memory and said distributed processors or said disk drive memory.

Claim 13

The apparatus of claim 9, wherein data transfers between said cache memory and said processors occurs at a first data rate and data transfers between said cache memory and said disk drive memory occur at a second data rate different from said first data rate.

Claim 14

In a multiprocessing system, a partitionable cache store interface to a shared disk drive memory, comprising: a cache storage memory having a data input and output connected to a data bus communicating in common with a plurality of distributed processors and with said disk memory, for storing data sets for each of said processors in mutually exclusive partitions; a direct memory access (DMA) controller having a control line connected to each of said processors and to said disk drive memory, for receiving bus allocation demands from said processors and allocating time divided access for selected ones of said processors to said data bus for transferring data to or from corresponding ones of said partitions in said cache storage memory; a plurality of word counters in said DMA controller, each having an input respectively connected to a corresponding one of said processors, for counting the quantity of data stored in each corresponding one of said partitions of said cache storage memory and initiating a bus allocation demand for said disk drive memory to obtain time divided access to said data bus for transferring data from said corresponding partitions to said disk drive memory; said cache storage memory including a command word partition for the storage of data transfer command words received over said data bus on a time divided basis from said distributed processors; a local control processor having a data line connected to said data input and output of said cache storage memory and a control line connected to said DMA controller, for accessing and decoding said command words from said cache memory; said local control processor signalling said DMA controller in response to one of said decoded command words, to control data transfers between said cache storage memory and said distributed processors or said disk drive memory; whereby data can be transferred between said plurality of processors and said cache memory and between said cache memory and said disk drive memory on a time divided basis.

Claim 15

In a multiprocessing system, a partitionable cache store interface to a shared disk drive memory, comprising: a cache storage memory having a data input and output connected to a data bus communicating in common with a plurality of distributed processors and with said disk memory, for storing data sets for each of said processors in mutually exclusive partitions; a direct memory access (DMA) controller having a control line connected to each of said processors and to said disk drive memory, for receiving bus allocation demands from said processors and allocating time divided access for selected ones of said processors to said data bus for transferring data to or from corresponding ones of said partitions in said cache storage memory; a plurality of word counters in said DMA controller, each having an input respectively connected to a corresponding one of said processors, for counting the quantity of data stored in each corresponding one of said partitions of said cache storage memory and initiating a bus allocation demand for said disk drive memory to obtain time divided access to said data bus for transferring data from said corresponding partitions to said disk drive memory; said cache storage memory including a command word partition for the storage of data transfer command words received over said data bus on a time divided basis from said distributed processors; a local control processor having a data line connected to said data input and output of said cache storage memory and a control line connected to said DMA controller, for accessing and decoding said command words from said cache memory; said local control processor signalling said DMA controller in response to one of said decoded command words, to control data transfers between said cache storage memory and said distributed processors or said disk drive memory; whereby data can be transferred between said plurality of processors and said cache memory and between said cache memory and said disk drive memory on a time divided basis.

Claim 16

A multiprocessing system including a partitionable cache store interface to a shared disk drive memory, comprising: a plurality of host adapters, each respectively connected between one of a plurality of distributed data processors and a common data bus; a disk adapter connected between said disk drive memory and said common data bus; a cache storage memory having a data input and output connected to said data bus for storing data sets for each of said processors in mutually exclusive partitions; a direct memory access (DMA) controller having a control line connected to each of said host adapters and to said disk adapter, for receiving bus allocation demands from said processors and allocating time divided access for selected ones of said processors to said data bus for transferring data to or from corresponding ones of said partitions in said cache storage memory; a plurality of word counters in said DMA controller, each having an input respectively connected to a corresponding one of said host adapters, for counting the quantity of data stored in each corresponding one of said partitions of said cache storage memory and initiating a bus allocation demand for said disk drive memory to obtain time divided access to said data bus for transferring data from said corresponding partitions to said disk drive memory; said cache storage memory including a command word partition for the storage of data transfer command words received over said data bus on a time divided basis from said distributed processors; a local control processor having a data line connected to said data input and output of said cache storage memory and a control line connected to said DMA controller, for accessing and decoding said command words from said cache memory; said local control processor signalling said DMA controller in response to one of said decoded command words, to control data transfers between said cache storage memory and said host adapters or said disk adapter; whereby data can be transferred between said plurality of processors and said cache memory and between said cache memory and said disk drive memory on a time divided basis.

Claim 17

A multiprocessing system including a partitionable cache store interface to a shared disk drive memory, comprising: a plurality of host adapters, each respectively connected between one of a plurality of distributed data processors and a common data bus; a disk adapter connected between said disk drive memory and said common data bus; a cache storage memory having a data input and output connected to said data bus for storing data sets for each of said processors in mutually exclusive partitions; a direct memory access (DMA) controller having a control line connected to each of said host adapters and to said disk adapter, for receiving bus allocation demands from said processors and allocating time divided access for selected ones of said processors to said data bus for transferring data to or from corresponding ones of said partitions in said cache storage memory; a plurality of word counters in said DMA controller, each having an input respectively connected to a corresponding one of said host adapters, for counting the quantity of data stored in each corresponding one of said partitions of said cache storage memory and initiating a bus allocation demand for said disk drive memory to obtain time divided access to said data bus for transferring data from said corresponding partitions to said disk drive memory; said cache storage memory including a command word partition for the storage of data transfer command words received over said data bus on a time divided basis from said distributed processors; a local control processor having a data line connected to said data input and output of said cache storage memory and a control line connected to said DMA controller, for accessing and decoding said command words from said cache memory; said local control processor signalling said DMA controller in response to one of said decoded command words, to control data transfers between said cache storage memory and said host adapters or said disk adapter; whereby data can be transferred between said plurality of processors and said cache memory and between said cache memory and said disk drive memory on a time divided basis.