US4357707A
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US
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Digital phase lock loop for flexible disk data recovery system
Assignee: PERTEC PERIPHERALS CORP
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Filing: 1979-04-11
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Granted: 1982-11-02
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Expires: 1999-04-11
Abstract
Abstract A digital phase lock loop system used in conjunction with a flexible disk drive controller for recovering data information from either single density or double density serially encoded data. More specifically, a phase lock system is disclosed in which data bit windows and clock bit windows are defined by a plurality of phase clock cycles. A circuit is provided for determining during which phase clock cycle a bit occurs, an adjustment being made to the duration of its corresponding bit window and thus to the initiation time of a subsequent bit window which will tend to position the window so that it will be centered about its corresponding bit. In a specific embodiment for double density encoded data, a circuit is provided whereby the subsequent bit window is positioned in accordance with the position of the current bit within its corresponding window and the position of a preceding bit within its corresponding bit window. In addition, the invention provides a circuit whereby a position of each bit within its corresponding window is counted, the net count being indicative of the number of bits appearing in the second half of their corresponding bit windows less the number of bits appearing in the first half of their corresponding bit windows. A bias phase adjustment signal is generated for altering the duration of a bit window until the net count approaches zero. This altering provides for automatic compensation of variations in disk rotation speed and/or recording speed variations.
Inventors
- 👤 Dale E. Delury
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:42
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1407; G11B20/1419; G11B20/1423
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
174 words
A system for generating a signal in phase lock with data bits within an encoded bit stream having data bits and clock bits, comprising: means for providing a phase clock signal formed of a sequence of phase clock cycles; means for assigning a discrete phase count from within the range O-N of positive integers to each phase clock cycle; means responsive to said phase clock signal for producing a sequence of bit windows, each corresponding with a bit in said bit stream, each bit window having a variable duration during which a plurality of phase clock cycles occur; each bit window duration being initiated responsive to the occurrence of a phase clock cycle assigned a second discrete phase count; means for determining the position of a bit in said bit stream with respect to the phase clock cycles within the bit window corresponding therewith; and means for selectively varying the number of phase clock cycles occurring during a bit window duration responsive to the position within said bit window of the bit corresponding therewith.
Claim 2
Independent Claim
174 words
A system for generating a signal in phase lock with data bits within an encoded bit stream having data bits and clock bits, comprising: means for providing a phase clock signal formed of a sequence of phase clock cycles; means for assigning a discrete phase count from within the range O-N of positive integers to each phase clock cycle; means responsive to said phase clock signal for producing a sequence of bit windows, each corresponding with a bit in said bit stream, each bit window having a variable duration during which a plurality of phase clock cycles occur; each bit window duration being initiated responsive to the occurrence of a phase clock cycle assigned a second discrete phase count; means for determining the position of a bit in said bit stream with respect to the phase clock cycles within the bit window corresponding therewith; and means for selectively varying the number of phase clock cycles occurring during a bit window duration responsive to the position within said bit window of the bit corresponding therewith.
Claim 3
Dependent Claim
18 words
The system of claim 1 wherein said bit windows comprise alternating data bit windows and clock bit windows.
Claim 4
Dependent Claim
54 words
The system of claim 1 in which a nominal bit window is defined by a predetermined plurality of phase clock cycles and including means responsive to the positions of selected bits within their respective corresponding bit windows for lengthing or shortening said nominal bit window by multiples of one-half of a phase clock cycle.
Claim 5
Dependent Claim
38 words
The system of claim 1 further including means for varying the duration of said phase clock cycles occuring during the duration of a bit window responsive to the position within said bit window of the bit corresponding therewith.
Claim 6
Dependent Claim
49 words
The system of claim 4 wherein said means for varying the duration of said phase clock cycles defining a bit window comprises means for varying the duration of said phase clock cycles responsive to the positions within their respective bit windows of two selected bits in said bit stream.
Claim 7
Dependent Claim
53 words
The system of claim 1 wherein said means for selectively varying the number of phase clock cycles occurring during the duration of a bit window comprises means for varying the number of said phase clock cycles responsive to the positions within their respective bit windows of two selected bits in said bit stream.
Claim 8
Dependent Claim
148 words
In combination with a flexible disk data recovery system wherein an encoded bit stream having data bits and clock bits is obtained from a flexible disk, a means for generating a signal in phase lock with said data bits, comprising: means for providing a phase clock signal formed of a sequence of phase clock cycles; means responsive to said phase clock signal for producing a bit window to correspond with each bit in said bit stream; each of said bit windows having a variable duration defined by a plurality of said phase clock cycles; means for providing a signal indicative of the position of a selected bit with respect to the phase clock cycles within the bit window corresponding therewith; and means for selectively varying the number of phase clock cycles defining a bit window responsive to the position within said bit window of the bit corresponding therewith.
Claim 9
Dependent Claim
148 words
In combination with a flexible disk data recovery system wherein an encoded bit stream having data bits and clock bits is obtained from a flexible disk, a means for generating a signal in phase lock with said data bits, comprising: means for providing a phase clock signal formed of a sequence of phase clock cycles; means responsive to said phase clock signal for producing a bit window to correspond with each bit in said bit stream; each of said bit windows having a variable duration defined by a plurality of said phase clock cycles; means for providing a signal indicative of the position of a selected bit with respect to the phase clock cycles within the bit window corresponding therewith; and means for selectively varying the number of phase clock cycles defining a bit window responsive to the position within said bit window of the bit corresponding therewith.
Claim 10
Dependent Claim
34 words
The system of claim 7 further including means for varying the duration of said phase clock cycles defining a bit window responsive to the position within said bit window of the bit corresponding therewith.
Claim 11
Dependent Claim
50 words
The system of claim 8 wherein said means for selectively varying the duration of said phase clock cycles defining a bit window comprises means for varying the duration of said phase clock cycles responsive to the positions within their respective bit windows of two selected bits in said bit stream.
Claim 12
Dependent Claim
49 words
The system of claim 7 wherein said means for selectively varying the number of phase clock cycles defining a bit window comprises means for varying the number of said phase clock cycles responsive to the positions within their respective bit windows of two selected bits in said bit stream.
Claim 13
Independent Claim
132 words
A system for generating a signal in phase lock with data bits within an encoded bit stream having data bits and clock bits comprising: means for providing a phase clock signal formed of a sequence of phase clock cycles; means responsive to said phase clock signal for providing a bit window to correspond with each bit in said bit stream; each of said bit windows having a variable duration defined by a plurality of said phase clock cycles; means for providing a signal indicative of the position of a selected bit with respect to the phase clock cycles within the bit window corresponding therewith; and means for selectively varying the duration of phase clock cycles defining a bit window responsive to the position within the bit window of the bit corresponding therewith.
Claim 14
Independent Claim
132 words
A system for generating a signal in phase lock with data bits within an encoded bit stream having data bits and clock bits comprising: means for providing a phase clock signal formed of a sequence of phase clock cycles; means responsive to said phase clock signal for providing a bit window to correspond with each bit in said bit stream; each of said bit windows having a variable duration defined by a plurality of said phase clock cycles; means for providing a signal indicative of the position of a selected bit with respect to the phase clock cycles within the bit window corresponding therewith; and means for selectively varying the duration of phase clock cycles defining a bit window responsive to the position within the bit window of the bit corresponding therewith.
Claim 15
Dependent Claim
46 words
The system of claim 11 wherein said means for providing a signal indicative of the position of a selected bit with respect to the phase clock cycles within the bit window corresponding therewith includes means for identifying a phase clock cycle essentially coincident with said bit.
Claim 16
Independent Claim
119 words
A method of generating a signal in phase lock with bits within an encoded bit stream having data bits and clock bits, comprising the steps of: providing a phase clock signal formed of a sequence of phase clock cycles; producing a bit window to correspond with each bit in said bit stream; each of said bit windows having a variable duration defined by a plurality of said phase clock cycles; determining the position of a bit in said bit stream with respect to the phase clock cycles within the bit window corresponding therewith; and selectively varying the number of phase clock cycles defining a bit window responsive to the position within said bit window of the bit corresponding therewith.
Claim 17
Independent Claim
119 words
A method of generating a signal in phase lock with bits within an encoded bit stream having data bits and clock bits, comprising the steps of: providing a phase clock signal formed of a sequence of phase clock cycles; producing a bit window to correspond with each bit in said bit stream; each of said bit windows having a variable duration defined by a plurality of said phase clock cycles; determining the position of a bit in said bit stream with respect to the phase clock cycles within the bit window corresponding therewith; and selectively varying the number of phase clock cycles defining a bit window responsive to the position within said bit window of the bit corresponding therewith.
Claim 18
Dependent Claim
50 words
The method of claim 13 wherein said step of selectively varying the number of phase clock cycles defining a bit window comprises the step of varying the number of said phase clock cycles responsive to the positions within their respective bit windows of two selected bits in said bit stream.
Claim 19
Dependent Claim
20 words
The method of claim 13 further comprising the step of tending to center each bit window abouts its corresponding bit.
Claim 20
Dependent Claim
105 words
In combination with a data source providing a stream of bits, means for generating a signal comprised of bit windows occurring in synchronism with said bits, said signal generating means comprising: means for producing a first signal comprising successive transitions to define successive bit windows each having a duration defined by the interval between successive transitions; means for producing a second signal indicative of the interval between the occurrence time of each transition initiating a bit window and the occurrence time of a bit within that same bit window; and means responsive to said second signal for adjusting the duration of that same bit window.
Claim 21
Dependent Claim
105 words
In combination with a data source providing a stream of bits, means for generating a signal comprised of bit windows occurring in synchronism with said bits, said signal generating means comprising: means for producing a first signal comprising successive transitions to define successive bit windows each having a duration defined by the interval between successive transitions; means for producing a second signal indicative of the interval between the occurrence time of each transition initiating a bit window and the occurrence time of a bit within that same bit window; and means responsive to said second signal for adjusting the duration of that same bit window.
Claim 22
Dependent Claim
27 words
The combination of claim 16 wherein said adjusting means includes means for selecting the occurrence time of the transition succeeding said transition initiating said same bit window.
Claim 23
Dependent Claim
124 words
In a system for obtaining data bits from an encoded bit stream containing data bits and clock bits, the improvement comprising: means for providing a phase clock signal formed of a sequence of ordered phase clock cycles; means responsive to said phase clock signal for defining nominal bit windows, each being defined by a predetermined plurality of said phase clock cycles and each corresponding with a different one of said data and clock bits; means for determining the position of a selected bit within its corresponding bit window by identifying the order of a phase clock cycle essentially coincident therewith; and means for adjusting the initiation time of a bit window responsive to the positions of two preceding bits within their respective bit windows.
Claim 24
Dependent Claim
124 words
In a system for obtaining data bits from an encoded bit stream containing data bits and clock bits, the improvement comprising: means for providing a phase clock signal formed of a sequence of ordered phase clock cycles; means responsive to said phase clock signal for defining nominal bit windows, each being defined by a predetermined plurality of said phase clock cycles and each corresponding with a different one of said data and clock bits; means for determining the position of a selected bit within its corresponding bit window by identifying the order of a phase clock cycle essentially coincident therewith; and means for adjusting the initiation time of a bit window responsive to the positions of two preceding bits within their respective bit windows.
Claim 25
Dependent Claim
31 words
The system of claim 18 further comprising means responsive to the positions of selected bits within their respective corresponding bit windows for substantially centering said bit windows about their corresponding bits.
Claim 26
Dependent Claim
175 words
The system of claim 19 wherein said means for substantially centering comprises means for altering the duration of a bit window in accordance with a predetermined frequency bias adjustment table and further comprising; a frequency error counter; means for decrementing said frequency error counter when a bit is in a first position within its corresponding bit window and for incrementing said counter when a bit is in a second position within its corresponding bit window; a bias memory having a plurality of bias memory locations each of which stores an entry of said frequency bias adjustment table; means for accessing said bias memory locations in accordance with the count in said frequency error counter; means responsive to the count in said frequency error counter for generating bias phase adjustment signals having a frequency of occurence determined by said frequency bias adjustment table; and means responsive to said bias phase adjustment signals for adjusting the duration of bit windows occurring concurrent with said bias phase adjustment signals by multiples of one-half of a phase clock cycle.
Claim 27
Dependent Claim
90 words
The system of claim 20 wherein said means for adjusting the duration of bit windows comprises: a control memory having a plurality of control memory locations accessable by said phase adjustment signals, each of said control memory locations storing a duration control instruction for controlling the duration of a bit window; means for selectively varying the number of phase clock cycles defining a bit window in accordance with selected duration control instructions; and means for altering the duration of selected phase clock cycles in accordance with selected duration control instructions.
Claim 28
Dependent Claim
30 words
The system of claim 18 wherein said means for adjusting comprises means for altering the duration of a bit window in accordance with a predetermined first bit window alteration table.
Claim 29
Dependent Claim
98 words
The system of claim 22 wherein said means for altering comprises: means for storing phase count information identifying the positions of two selected bits with respect to the initiation time of their respective bit windows; a plurality of control memory locations, each of which contains an entry of said bit window alteration table; means for accessing said plurality of control memory locations in accordance with said phase count information; and means for changing the phase of said phase clock signal at the end of a phase clock cycle responsive to said entries accessed from said control memory locations.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1985-11-01 | 1986-05-03 | 1986-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-11-01 | 1990-05-03 | 1990-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-11-01 | 1994-05-03 | 1994-11-02 | $7700.00 | Window Closed / Lapsed |