US4180701A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase lock loop for data decoder clock generator
Assignee: Ampex Corp
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Filing: 1977-01-28
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Granted: 1979-12-25
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Expires: 1997-01-28
Abstract
Abstract Apparatus is disclosed for phase locking the output of a voltage controlled oscillator to a self-clocking data pulse stream occurring at a basic predetermined rate, the data stream being of the kind in which the data content is determined by a signal state change located in one of two positions within the data cell interval of the data stream. Each signal state change is defined by a narrow data pulse. The oscillator is controlled by a first means to operate at the predetermined rate when the data pulses are not present and by a second means when the data pulses are present. The second means compares one selected transition of the clock pulses of the oscillator output signal to the position of the data pulse and provides a variable control voltage to the oscillator to adjust its phase so that the the selected clock pulse transition is synchronized to occur at the midpoint of the data pulses.
Inventors
- 👤 Kenneth Louth
- 👤 Luigi C. Gallo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:29
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/79; H04N9/80; H04N9/808; G; G11; G11B; G11B17/00; G11B17/005; H04N5/00; H04N5/76; H04N5/78; H04N5/781; H04N5/91; H04N5/93; H04N5/935; G11B2220/00; G11B2220/20
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
352 words
Apparatus for phase locking a clock signal to a self clocking data stream having data distributed in regularly occurring data cell intervals, said data defined by a data pulse occurring in the data cell interval with the data pulse interval less than the cell interval, said apparatus comprising: an oscillator for generating said clock signal, said oscillator responsive to control signals to generate a clock signal of a frequency and phase varying in accordance with the control signal applied thereto; first means coupled to said oscillator for supplying said control signal in response to a current being applied thereto; second means for supplying a predetermined level of current to said first means, said second means responsive to said data stream to supply said predetermined level of current when data pulses are absent from said data stream, said first means responsive to said predetermined level of current to supply a control signal to said oscillator that maintains the frequency of said clock signal substantially at a predetermined rate, said second means rendered inoperative in response to the presence of said data pulses in said data stream; and third means for supplying a variable interval of current to said first means in response to the occurrence of said data pulses and said clock signal, said third means enabled to supply current to said first means in response to the occurrence of data pulses and disabled from supplying current to said first means in response to the occurrence of a selected signal transition of said clock signal during the interval of said data pulse, the interval of current supplied by said third means varying with the time of occurrence of said selected signal transition during said data pulse interval, said first means responsive to the interval of current supplied by said third means to supply another control signal to said oscillator that maintains the frequency and phase of said clock signal so that said selected signal transition of said clock signal is maintained at the midpoint of said data pulse interval, said third means rendered inoperative in response to the absence of said data pulses.
Claim 2
Dependent Claim
352 words
Apparatus for phase locking a clock signal to a self clocking data stream having data distributed in regularly occurring data cell intervals, said data defined by a data pulse occurring in the data cell interval with the data pulse interval less than the cell interval, said apparatus comprising: an oscillator for generating said clock signal, said oscillator responsive to control signals to generate a clock signal of a frequency and phase varying in accordance with the control signal applied thereto; first means coupled to said oscillator for supplying said control signal in response to a current being applied thereto; second means for supplying a predetermined level of current to said first means, said second means responsive to said data stream to supply said predetermined level of current when data pulses are absent from said data stream, said first means responsive to said predetermined level of current to supply a control signal to said oscillator that maintains the frequency of said clock signal substantially at a predetermined rate, said second means rendered inoperative in response to the presence of said data pulses in said data stream; and third means for supplying a variable interval of current to said first means in response to the occurrence of said data pulses and said clock signal, said third means enabled to supply current to said first means in response to the occurrence of data pulses and disabled from supplying current to said first means in response to the occurrence of a selected signal transition of said clock signal during the interval of said data pulse, the interval of current supplied by said third means varying with the time of occurrence of said selected signal transition during said data pulse interval, said first means responsive to the interval of current supplied by said third means to supply another control signal to said oscillator that maintains the frequency and phase of said clock signal so that said selected signal transition of said clock signal is maintained at the midpoint of said data pulse interval, said third means rendered inoperative in response to the absence of said data pulses.
Claim 3
Dependent Claim
129 words
Apparatus as defined in claim 1 wherein said oscillator is a voltage controlled oscillator responsive to voltage level control signals to generate said clock signal of variable frequency and phase; and said first means is responsive to applied current to supply a voltage level control signal to said voltage controlled oscillator, said first means is reponsive to said predetermined level of current supplied by said second means to supply a predetermined voltage level control signal to said voltage controlled oscillator that maintains a frequency of said clock signal substantially at said predetermined rate, and said first means is responsive to the interval of current supplied by the third means to supply another voltage level control signal which voltage level varies in accordance with the duration of the current interval.
Claim 4
Dependent Claim
158 words
Apparatus as defined in claim 2 wherein said second means includes a first current source coupled to receive clock pulses obtained from said voltage controlled oscillator and said data pulses and responsive to said clock pulses in the absence of data pulses in said data stream to supply said predetermined current level signal to said first means; and said third means includes a second current source and a switch means providing alternate current paths for current supplied by said second current source, a first alternate current path coupling said second current source to said first means, a second alternate current path coupling said second current source to by-pass said first means, said switch means responsive to the occurrence of a data pulse to couple said second current source to said first alternate path and to the occurrence of a selected signal level transition in said clock pulse to couple said second current source to said second alternate path.
Claim 5
Dependent Claim
32 words
Apparatus as defined in claim 3 wherein said second current source supplies current at a level of about two times greater than the level of current supplied by the first current source.
Claim 6
Dependent Claim
81 words
Apparatus as defined in claim 2 wherein said data pulses and clock signal are rectangular pulses with leading and trailing level transition edges, said third means enabled to supply current to said first means in response to each data pulse, said third means disabled from supplying current to said first means in response to the first to occur as between the termination of said enabling data pulse and the occurrence of a selected level transition edge of said clock pulse signal.
Claim 7
Dependent Claim
109 words
Apparatus as defined in claim 5 wherein data pulses occur at boundary edges and midpoints of data cell intervals of said data stream, the frequency of the clock pulses generated by said oscillator is equal to two times the data cell interval rate, each clock pulse is coupled to said second means and third means to terminate the supply of current to the first means by said third means if previously enabled to supply said interval of current by a data pulse and to enable the supply of current to the first means by said second means if said third means not enabled to supply said interval of current.
References Cited (Backward Citations)
US3896265A
Cited
US3991378A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-12-24 | 1983-06-25 | 1983-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-12-24 | 1987-06-25 | 1987-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-12-24 | 1991-06-25 | 1991-12-25 | $7700.00 | Window Closed / Lapsed |