US4313809A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of reducing edge current leakage in N channel silicon-on-sapphire devices
Assignee: Intersil Corp
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Filing: 1980-10-15
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Granted: 1982-02-02
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Expires: 2000-10-15
Abstract
Abstract A novel process for improving the operation of silicon-on-sapphire devices by removing or minimizing edge current leakage. The reduction in leakage current is accomplished by subjecting the completed device to a sputtering operation and depositing thereon a layer of, for example, aluminum which is subsequently removed prior to scribing and dicing.
Inventors
- 👤 Carl W. Benyon, Jr.
- 👤 John J. O'Neill, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:24
CPC Classifications
H; H10; H10W; H10W42/00; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6706; H10D30/6758; H10D30/6759; H10P; H10P54/00; Y; Y10; Y10S; Y10S438/00; Y10S438/91; Y10S438/958
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
98 words
In a process for reducing the zero gate voltage leakage of an MOS device, wherein a plurality of devices are initially formed on a wafer of insulating material, each device having source and drain regions, first and second interconnecting leads in ohmic contact with respective source and drain regions, third interconnecting leads capacitively coupled to respective channel regions, and a passivating layer covering each of the devices on the wafer, the improved process comprising the steps of: sputtering a layer of metal on the passivating layer completely covering each device on the wafer; and removing the sputtered layer.
Claim 2
Dependent Claim
98 words
In a process for reducing the zero gate voltage leakage of an MOS device, wherein a plurality of devices are initially formed on a wafer of insulating material, each device having source and drain regions, first and second interconnecting leads in ohmic contact with respective source and drain regions, third interconnecting leads capacitively coupled to respective channel regions, and a passivating layer covering each of the devices on the wafer, the improved process comprising the steps of: sputtering a layer of metal on the passivating layer completely covering each device on the wafer; and removing the sputtered layer.
Claim 3
Dependent Claim
13 words
The process of claim 1, wherein: the sputtered layer of metal is aluminum.
Claim 4
Dependent Claim
22 words
The process of claim 2, wherein: the insulating substrate is selected from the group consisting of sapphire, monocrystalline aluminum oxide and spinel.
Claim 5
Dependent Claim
18 words
The process of claim 3, wherein: the aluminum layer is sputtered to a thickness of about 1 micrometer.
Claim 6
Dependent Claim
24 words
The process of claim 4 comprising the further steps of: performing the step of sputtering in an inert atmosphere maintained at about 2.5 millitorr.
Claim 7
Dependent Claim
17 words
The process of claim 5, wherein: the aluminum is deposited at a rate of about 160 angstroms/min.
References Cited (Backward Citations)
US3890632A
Cited
US4111775A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-02-01 | 1985-08-03 | 1986-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-02-01 | 1989-08-03 | 1990-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-02-01 | 1993-08-03 | 1994-02-02 | $7700.00 | Window Closed / Lapsed |