Patent US4306289A successfully refreshed from Google Patents.
US4306289A
Expired / Lapsed
US
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Digital computer having code conversion apparatus for an encrypted program
Assignee: AT&T Inc
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Filing: 1980-02-04
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Granted: 1981-12-15
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Expires: 2000-02-04
Abstract
Abstract The architecture of a conventional digital computer, for example, a microprocessor, is modified by interposing a multiplexer (31), a logic array (32) and a demultiplexer (33) between the instruction register (17) and instruction decoder (18). The logic array "scrambles" the bits in each instruction code; however, if the program to be run is priorly encrypted with this "scrambling" in mind, it will run normally. On the other hand, if the encrypted program is copied, the copied program will not run on an unmodified computer.
Inventors
- 👤 Robert M. Lumley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:20
CPC Classifications
G; G06; G06F; G06F21/00; G06F21/70; G06F21/71; G06F21/72; G06F21/10; G06F21/101; G06F21/12; G06F21/121; G06F21/123
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
159 words
An improved electronic digital computer comprising: an internal data bus; a register array coupled to said internal bus and including a plurality of general purpose data registers; an accumulator connected to said internal data bus; an arithmetic logic unit connected to said accumulator and to said internal data bus for performing logical operations on the data stored in said accumulator and in said general purpose registers; an instruction register connected to said internal data and adapted to receive program instruction codes; and an instruction decoder connected to said instruction register and responsive to selected ones of said program instruction codes, WHEREIN THE IMPROVEMENT COMPRISES means, within the electronic digital computer, interposed between said instruction register and said instruction decoder, for selectively transforming the bit pattern of a program instruction code into a second instruction code thereby enabling said computer to selectively respond to sequences of program instruction codes which have priorly been encrypted as instruction codes in non-standard format.
Claim 2
Dependent Claim
159 words
An improved electronic digital computer comprising: an internal data bus; a register array coupled to said internal bus and including a plurality of general purpose data registers; an accumulator connected to said internal data bus; an arithmetic logic unit connected to said accumulator and to said internal data bus for performing logical operations on the data stored in said accumulator and in said general purpose registers; an instruction register connected to said internal data and adapted to receive program instruction codes; and an instruction decoder connected to said instruction register and responsive to selected ones of said program instruction codes, WHEREIN THE IMPROVEMENT COMPRISES means, within the electronic digital computer, interposed between said instruction register and said instruction decoder, for selectively transforming the bit pattern of a program instruction code into a second instruction code thereby enabling said computer to selectively respond to sequences of program instruction codes which have priorly been encrypted as instruction codes in non-standard format.
Claim 3
Dependent Claim
96 words
The computer according to claim 1, wherein said transforming means comprises: a first multiplexer connected to the output of said instruction register; a logic array circuit connected to the output of said first multiplexer for producing a predetermined translation between the bits comprising the instruction code input thereto and the instruction code output therefrom; a second multiplexer connected to the output of said logic array circuit; and means for activating said first and second multiplexers such that the flow of program instruction code from said instruction register to said instruction decoder selectively bypasses said logic circuit.
Claim 4
Dependent Claim
52 words
The computer according to claim 2, wherein said logic array circuit comprises a plurality of logic gates interconnected in accordance with a predetermined pattern and interposed between the input of said logic array circuit and the output thereof for producing a predetermined fixed translation of the bits comprising said program instruction code.
Claim 5
Dependent Claim
76 words
The computer according to claim 2, wherein said logic array circuit comprises: a plurality of logic subarray circuits, each comprising a plurality of logic gates interconnected in accordance with a predetermined pattern, said logic subarray circuits being interposed between the input of said logic array circuit and the output thereof; and means coupled to the logic subarray circuits for selectively routing the flow of program instruction codes through a particular one of said logic subarray circuits.
Claim 6
Dependent Claim
46 words
The computer according to claim 4, further comprising: means, responsive to a control signal from said instruction decoder, for selectively routing the flow of program instruction codes through different ones of said plurality of logic subarray circuits during execution of a sequence of program instruction codes.
Claim 7
Dependent Claim
90 words
The apparatus according to claim 2, wherein said logic array circuit comprises: a plurality of logical elements each having at least two inputs, one of which connects to the corresponding bit input of said program instruction code; and a pseudo-random generator having a plurality of outputs each of which connects to a corresponding other input of said logic elements, whereby the bit translation effected between an incoming program instruction code and the output program instruction code changes, in a pseudo-random fashion, at predetermined intervals during the execution of said program.
Claim 8
Dependent Claim
76 words
The apparatus according to claim 2, wherein said logic array circuit comprises: a read-only memory having a plurality of address lines and a corresponding plurality of data output lines, said address lines being connected to said instruction register via said first multiplexer and said data output lines being connected to said instruction decoder via said second multiplexer whereby the selective bit transposition is effected by means of a look-up table priorly stored in said read-only memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-12-14 | 1985-06-15 | 1985-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-12-14 | 1989-06-15 | 1989-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-12-14 | 1993-06-15 | 1993-12-15 | $7700.00 | Window Closed / Lapsed |