US4291404A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Automatic circuit tester with improved voltage regulator
Assignee: Lockheed Martin Corp
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Filing: 1979-11-20
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Granted: 1981-09-22
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Expires: 1999-11-20
Abstract
Abstract A battery operated microcomputer controlled programmable circuit testing device. Standard I/O/memory devices (25a, 25b) are connected to a microcomputer (20) in such a manner as to treat the I/O ports (46, 47) of the I/O memory devices as programmable interfaces and to allow pin receptors in a socket (10) to be individually programmed as inputs or outputs. Double detent switches (12, 13) connected to testable inputs T0, T1, 45) the microcomputer are used to scroll a roll table containing names of devices which may be tested in either a forward or a reverse direction at two different speeds. Compression of the roll table storage is provided by storing only data which differs from the previous element. A power supply (17) having a regulator featuring a series pass transistor (150) connected as a common collector amplifier is shown. The power supply is turned on and off by switching devices (11, 151, 160, 159) which control base current only to a transistor switch (155, 170) operating analog circuitry (157) which controls the pass transistor. Microcomputer control (181) of the power supply and self latching embodiments are also shown. The power supply shown herein can successfully regulate output voltages which differ from the raw DC input by no more than the saturation voltages of series pass transistor.
Inventors
- 👤 William G. Steiner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 17:16
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31915
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
302 words
An automatic circuit testing apparatus comprising in combination: a receptacle means for providing electrical contact with a unit under test; at least one integrated circuit input/output memory device including memory, at least one input/output port, a data bus, a port/memory selector pin connected to a signal source corresponding to selection of memory, a read input responsive to an active state thereon to read onto said data bus data from said memory when said port/memory selector pin is in a first state and to read onto said data bus data from said input/output port when said port/memory selector pin is in a second state, a port read input responsive to an active state thereon to cause data present at said input/output port to be provided onto said data bus and a port write input responsive to an active state thereon to write data present on said data bus to said input/output port; a microcomputer including a microcomputer data bus, a write output for providing an active output state in response to said microcomputer executing an instruction to write data present on said computer data bus to an external device, a read output having an active state corresponding to said microcomputer accepting data from said computer data bus and a program store output having an active state corresponding to said computer seeking to accept data on said computer data bus as an instruction; means for electrically connecting said input/output port and said receptacle means; and means for connecting said microcomputer to said integrated circuit input/output memory device including a means for connecting said computer data bus to said data bus, a connection between said write output and said port write input, a connection between said read output and said port read input, and a connection between said program store output and said read input.
Claim 2
Dependent Claim
302 words
An automatic circuit testing apparatus comprising in combination: a receptacle means for providing electrical contact with a unit under test; at least one integrated circuit input/output memory device including memory, at least one input/output port, a data bus, a port/memory selector pin connected to a signal source corresponding to selection of memory, a read input responsive to an active state thereon to read onto said data bus data from said memory when said port/memory selector pin is in a first state and to read onto said data bus data from said input/output port when said port/memory selector pin is in a second state, a port read input responsive to an active state thereon to cause data present at said input/output port to be provided onto said data bus and a port write input responsive to an active state thereon to write data present on said data bus to said input/output port; a microcomputer including a microcomputer data bus, a write output for providing an active output state in response to said microcomputer executing an instruction to write data present on said computer data bus to an external device, a read output having an active state corresponding to said microcomputer accepting data from said computer data bus and a program store output having an active state corresponding to said computer seeking to accept data on said computer data bus as an instruction; means for electrically connecting said input/output port and said receptacle means; and means for connecting said microcomputer to said integrated circuit input/output memory device including a means for connecting said computer data bus to said data bus, a connection between said write output and said port write input, a connection between said read output and said port read input, and a connection between said program store output and said read input.
Claim 3
Dependent Claim
111 words
An automatic tester as recited in claim 1 wherein said integrated circuit input/output memory device is of a type in which said input/output port further comprises: an output latch including a buffered output for storing output data; a direction latch for controlling said buffered output; at least one pointing latch for steering data to said output latch in response to an active state on said port write input when said pointing latch is in a first state and alternately for steering data to said direction latch in response to an active state on said port write input when said pointing latch is in a second state different from said first state.
Claim 4
Dependent Claim
205 words
In an automated testing apparatus comprising a microcomputer including at least two inputs in a jump instruction of the instruction set of said microcomputer and a display, the improvement of: at least one double detent switch each including a pole connected to a signal source, a first contact connected to one of said testable inputs and a second contact connected to another of said testable inputs, said double detent switch being selectively operable to connect said pole to said first contact and alternately to connect said pole to both said first contact and said second contact; a memory accessed by said microcomputer, which memory stores data corresponding to a plurality of names in a plurality of name/address combinations in sequential addresses of said memory; program means accessed by said microcomputer for controlling the outputs of said microcomputer which outputs cause said display to provide a visible representation of said plurality of names in a predetermined order at a first rate in response to said pole contacting only said first contact and for providing to said display visible representations of said plurality of names in a predetermined order at a second rate in response to said pole contacting both said first contact and said second contact.
Claim 5
Dependent Claim
205 words
In an automated testing apparatus comprising a microcomputer including at least two inputs in a jump instruction of the instruction set of said microcomputer and a display, the improvement of: at least one double detent switch each including a pole connected to a signal source, a first contact connected to one of said testable inputs and a second contact connected to another of said testable inputs, said double detent switch being selectively operable to connect said pole to said first contact and alternately to connect said pole to both said first contact and said second contact; a memory accessed by said microcomputer, which memory stores data corresponding to a plurality of names in a plurality of name/address combinations in sequential addresses of said memory; program means accessed by said microcomputer for controlling the outputs of said microcomputer which outputs cause said display to provide a visible representation of said plurality of names in a predetermined order at a first rate in response to said pole contacting only said first contact and for providing to said display visible representations of said plurality of names in a predetermined order at a second rate in response to said pole contacting both said first contact and said second contact.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-21 | 1985-03-23 | 1985-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-21 | 1989-03-23 | 1989-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-21 | 1993-03-23 | 1993-09-22 | $7700.00 | Window Closed / Lapsed |