US3691531A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic computer with cyclic program memory
Assignee: Olivetti SpA
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Filing: 1970-06-18
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Granted: 1972-09-12
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Expires: 1990-06-18
Abstract
Abstract An electronic computer having a cyclic, serial access program storing tape memory and a random access memory for storing data. The random access memory also includes an input-output register and portions for storing the address of the next instruction to be executed in the program memory and an indirect address. A predetermined time after transferring an instruction to an instruction register the program memory checks to see if the execution of the instruction has been completed. If it hasn''t been, the motion of the tape is stopped until it is completed. Also provided are means for shifting the contents of a selected data memory register.
Inventors
- 👤 Fabrizio Saltini
- 👤 Vittorio Eccettuato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 19:26
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30032; G06F15/00; G06F15/02; G06F5/00; G06F5/01; G06F5/017
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
337 words
An electronic computer comprising: control logic for controlling the operation of the computer, a cyclic, serial access memory or storing the instructions of a program to be executed, said cyclic memory including a loop of magnetic tape having an information track on which the instructions are recorded, and an address associated with each instruction on said track, said instructions each being formed of a fixed number of characters, one of said characters being able to define the significance of the remaining characters, an instruction register for receiving the successive instructions of the program one at a time from said tape unit under the control of said control logic and for storing each instruction while it is being executed, a random access memory including a plurality of registers for storing data to be operated upon, a predetermined one of said data registers being used as an input-output register, an indirect address portion associated with said input-output register for storing an indirect address transferrable to a predetermined portion of said instruction register under the control of said control logic for use as an indirect address in the instruction then being executed, said predetermined portion of said instruction register containing at least one remaining character of the characters of said instruction, said at least one remAining character conditioning said predetermined portion of said instruction register for storing said indirect address according to the value of said at least one remaining character, said random access memory including a portion for storing the address on the tape of the instruction presently being executed, and an arithmetic unit for performing addition, subtraction and transfer operations between data stored in said input-output register and a selected one of the other registers of said random access memory under the control of said control logic, said random access memory and said arithmetic unit being responsive to commands from said control logic for incrementing the address stored in said tape address storing portion of said random access memory at the end of the execution of an instruction.
Claim 2
Dependent Claim
337 words
An electronic computer comprising: control logic for controlling the operation of the computer, a cyclic, serial access memory or storing the instructions of a program to be executed, said cyclic memory including a loop of magnetic tape having an information track on which the instructions are recorded, and an address associated with each instruction on said track, said instructions each being formed of a fixed number of characters, one of said characters being able to define the significance of the remaining characters, an instruction register for receiving the successive instructions of the program one at a time from said tape unit under the control of said control logic and for storing each instruction while it is being executed, a random access memory including a plurality of registers for storing data to be operated upon, a predetermined one of said data registers being used as an input-output register, an indirect address portion associated with said input-output register for storing an indirect address transferrable to a predetermined portion of said instruction register under the control of said control logic for use as an indirect address in the instruction then being executed, said predetermined portion of said instruction register containing at least one remaining character of the characters of said instruction, said at least one remAining character conditioning said predetermined portion of said instruction register for storing said indirect address according to the value of said at least one remaining character, said random access memory including a portion for storing the address on the tape of the instruction presently being executed, and an arithmetic unit for performing addition, subtraction and transfer operations between data stored in said input-output register and a selected one of the other registers of said random access memory under the control of said control logic, said random access memory and said arithmetic unit being responsive to commands from said control logic for incrementing the address stored in said tape address storing portion of said random access memory at the end of the execution of an instruction.
Claim 3
Dependent Claim
58 words
The computer of claim 1 wherein said serial access memory further includes means for sensing, a predetermined time after transferring an instruction to said instruction register, whether the execution of said transferred instruction by the comparator is completed, and means for halting the movement of said tape if the execution of said transferred instruction has not been completed.
Claim 4
Dependent Claim
51 words
The computer of claim 1 wherein said control logic includes means responsive to the presence of a jump instruction in said instruction register for transferring the portion of said jump instruction stored in a predetermined portion of said instruction register to said tape address storing portion of said random access memory.
Claim 5
Dependent Claim
243 words
The computer of claim 1 wherein said control logic is responsive to the presence of a multiplication instruction in said instruction register for performing a multiplication operation between a multiplicand in the input-output register and a multiplier in a first selected memory register and forming the product in a second selected memory register, and wherein said computer further includes: a first counter for counting the successive digit places of the first selected memory register starting from the least significant digit, a second counter for receiving under the control of said control logic the successive digits of the first selected memory register indicated by said first counter, said control logic including means for successively adding the contents of said input-output register to said second selected memory register and decrementing said second counter until said second counter arrives at zero, the arrival at zero by said second counter acting to increment said first counter, the incrementing of said first counter causing said control logic to transfer the next digit of the multiplier to said second counter, means for shifting the contents of said second selected register unit end-around one digit place toward the least significant digit upon the arrival at zero of said second counter, and means for counting the number of shifts by said shifting means and for terminating the multiplication operation when the least significant digit of the product is shifted into the least significant digit place of said second selected memory register.
Claim 6
Dependent Claim
204 words
An electronic computer having a control logic, an arithmetic unit operating under the control of said control logic, a program memory for storing program instructions to be executed by said logic and an address associated with each one of said instructions, and an instruction register controlled by said logic for causing each program instruction to be transferred from said program memory to said instruction register to be stored while it is being executed, wherein the improvement comprises: an indirect address register controlled by said logic for storing an indirect address and for transferring this indirect address to a predetermined portion of said instruction register, said logic conditioning said instruction register to use said indirect address for the instruction then being executed and for storing it in said program memory, each of said instructions being formed of a fixed numBer of characters, one of said characters being able to define the significance of the remaining characters, said predetermined portion of said instruction register containing at least one remaining character of the characters of said instruction, said at least one remaining character conditioning said predetermined portion of said instruction register for storing said indirect address according to the value of said at least one remaining character.
Claim 7
Dependent Claim
204 words
An electronic computer having a control logic, an arithmetic unit operating under the control of said control logic, a program memory for storing program instructions to be executed by said logic and an address associated with each one of said instructions, and an instruction register controlled by said logic for causing each program instruction to be transferred from said program memory to said instruction register to be stored while it is being executed, wherein the improvement comprises: an indirect address register controlled by said logic for storing an indirect address and for transferring this indirect address to a predetermined portion of said instruction register, said logic conditioning said instruction register to use said indirect address for the instruction then being executed and for storing it in said program memory, each of said instructions being formed of a fixed numBer of characters, one of said characters being able to define the significance of the remaining characters, said predetermined portion of said instruction register containing at least one remaining character of the characters of said instruction, said at least one remaining character conditioning said predetermined portion of said instruction register for storing said indirect address according to the value of said at least one remaining character.
Claim 8
Dependent Claim
53 words
A computer according to claim 5, comprising: a random access memory including a plurality of registers for storing data to be processed by said arithmetic unit, said indirect address register being formed of a portion of and being associated with a predetermined register of said random access memory used as an input-output register.
Claim 9
Dependent Claim
84 words
A computer according to claim 5, wherein said program memory is of the cyclic serial access type comprising a loop of magnetic tape having at least an information track on which said instructions are recorded and a portion on which the associated addresses are recorded, comprising means for incrementing the address stored in said serial access memory at the end of the execution of an instruction, said serial access memory and said arithmetic unit being controlled by said logic for operating said incrementing means.
Claim 10
Dependent Claim
58 words
A computer according to claim 7, characterized by means for sensing, a predetermined time after transferring an instruction to said instruction register, whether the execution of said transferred instructions has been executed, said sensing means controlling a means for halting the movement of said tape as long as the execution of said transferred instructions has not been completed.
Claim 11
Dependent Claim
59 words
A computer according to claim 8, wherein said logic includes means responsive to the presence of a jump instruction in said instruction register for transferring at least a part of said jump instruction to the portion of said tape storing the said address, said part of the jump instruction being stored in a predetermined portion of said instruction register.
Claim 12
Dependent Claim
148 words
A computer according to claim 6, wherein said logic is responsive to the presence of a multiplication instruction in said instruction register for multiplying a multiplicand stored in an input-output register by a multiplier stored in a first register of said random access memory and for accumulating the product in a second register of said random access memory, comprising: a first counter for counting the successive digit places a said first register starting from the least significant digit, and a second counter for receiving under the control of said logic the successive digits of said first register indicated by said first counter, said logic including means for decrementing said second counter until said second counter arrives at zero, the arrival at zero by said second counter acting to increment said first counter and causing said logic to transfer the next digit of the multiplier to said second counter.
Claim 13
Dependent Claim
72 words
A computer according to claim 10, comprising: means for shifting the contents of said second register end-around one digit place toward the least significant digit upon the arrival at zero of said second counter, and means for counting the number of shifts by said shifting means and for terminating the multiplication operation when the least significant digit of the product is shifted into the least significant digit place of said second register.
Claim 14
Dependent Claim
153 words
A computer according to claim 11, wherein said second register comprises a plurality of serially arranged cells, each one adapted to store one character, said shifting means comprising a single character register, and exchanging means controlled by said logic for exchanging a character from a selected cell of said second register with the character of said single character register, said exchanging means at first exchanging the character of said single character register with the character of the cell at one end of said second registEr and sequentially exchanging, after having performed said first exchange, the successive characters of said second register with the character each time stored in said single character register, starting from the character of the cell at the other end of said second register, said counting means indicating to said logic when all the characters of said second register have been exchanged for halting the operation of said exchanging means.
Claim 15
Dependent Claim
41 words
A computer according to claim 12, characterized in that said logic includes means for selectively inhibiting the transfer of the character at said one end of said second register to said single character register during the first exchange of the character.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-12 | 1976-03-13 | 1976-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-12 | 1980-03-13 | 1980-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-12 | 1984-03-13 | 1984-09-12 | $7700.00 | Window Closed / Lapsed |