US4245168A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integratable driver for liquid crystal displays and the like
Assignee: General Electric Co
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Filing: 1978-08-03
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Granted: 1981-01-13
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Expires: 1998-08-03
Abstract
Abstract A solid-state driver circuit having a relatively low output impedance, for supplying proper drive voltage to a liquid crystal display cell and the like, utilizes metal-oxide-semiconductor transistors and avalanche diodes to provide a driver requiring a relatively small area to facilitate integration of a large number of driver circuits upon a single integrated circuit chip.
Inventors
- 👤 Wesley K. Waldron
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:08
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/04; G09G3/16; G09G3/18; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/136277; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G3/3674; G09G3/3685
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
230 words
An integratable circuit for driving a load, comprising: first and second bus means for coupling respectively to first and second electrical potentials; an output terminal for coupling said circuit to said load; a first semiconductor device having first, second and third electrodes; said first electrode being coupled to said first bus means and said second and third electrodes being coupled together and to said output terminal to cause a substantially constant current to flow from said first electrode towards said output terminal; a second semiconductor device having first, second and third electrodes, with the magnitude of the impedance between said first and second electrodes being established by the magnitude of a voltage impressed between said second and third electrodes; said first and second electrodes being respectively coupled to said output terminal and said second bus means respectively; said third electrode receiving a voltage sufficient to reduce the impedance between said first and second electrodes for selectively causing substantially all of said substantially constant current to be conducted to said second bus means through said second semiconductor device responsive only to a first condition; and an avalanche diode coupled between said output terminal and said second bus means for establishing an essentially constant voltage therebetween only when said second semiconductor device responds to a condition other than said first condition and does not conduct substantial current toward said second bus means.
Claim 2
Dependent Claim
230 words
An integratable circuit for driving a load, comprising: first and second bus means for coupling respectively to first and second electrical potentials; an output terminal for coupling said circuit to said load; a first semiconductor device having first, second and third electrodes; said first electrode being coupled to said first bus means and said second and third electrodes being coupled together and to said output terminal to cause a substantially constant current to flow from said first electrode towards said output terminal; a second semiconductor device having first, second and third electrodes, with the magnitude of the impedance between said first and second electrodes being established by the magnitude of a voltage impressed between said second and third electrodes; said first and second electrodes being respectively coupled to said output terminal and said second bus means respectively; said third electrode receiving a voltage sufficient to reduce the impedance between said first and second electrodes for selectively causing substantially all of said substantially constant current to be conducted to said second bus means through said second semiconductor device responsive only to a first condition; and an avalanche diode coupled between said output terminal and said second bus means for establishing an essentially constant voltage therebetween only when said second semiconductor device responds to a condition other than said first condition and does not conduct substantial current toward said second bus means.
Claim 3
Dependent Claim
14 words
The driver circuit of claim 1, wherein said first and second devices are transistors.
Claim 4
Dependent Claim
14 words
The driver circuit of claim 2, wherein said transistors are of the MOS type.
Claim 5
Dependent Claim
13 words
The driver circuit of claim 3, wherein said transistors are both P-MOS transistors.
Claim 6
Dependent Claim
22 words
The driver circuit of claim 4, wherein said first device is a depletion-mode device and said second device is an enhancement-mode device.
Claim 7
Dependent Claim
106 words
In combination, a plurality of the driver circuits of claim 1, integrally fabricated in a single member of semiconductor material; each driver circuit having said first and second semiconductor devices being MOS transistors fabricated with a first type of semiconductor region forming each of the first and second electrodes thereof, the first electrode semiconductor region of the second device and the second electrode semiconductor region of the first device forming a single integral electrode region; said avalanche diode of each driver circuit being fabricated as a heavily doped region of the opposite type of semiconductor material underlying said single integral electrode region of that driver circuit.
Claim 8
Dependent Claim
140 words
In combination, a plurality of the driver circuits of claim 1, integrally fabricated in a single member of semiconductor material; each driver circuit having said first and second semiconductor devices being MOS transistors fabricated with a first type of semiconductor region forming each of the first and second electrodes thereof, the first electrode semiconductor region of the second device and the second electrode semiconductor region of the first device forming a single integral electrode region; said avalanche diode of each driver circuit being fabricated as a heavily doped region of the opposite type of semiconductor material underlying said single integral electrode region of that driver circuit; and a liquid crystal display having a like plurality of independently energizable electrodes; each electrode of said liquid crystal display being coupled to an output terminal of one of said plurality of driver circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-13 | 1984-07-14 | 1985-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-13 | 1988-07-14 | 1989-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-13 | 1992-07-14 | 1993-01-13 | $7700.00 | Window Closed / Lapsed |