Patent US4241398A successfully refreshed from Google Patents.
US4241398A
Expired / Lapsed
US
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Computer network, line protocol system
Assignee: RTX Corp
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Filing: 1978-09-29
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Granted: 1980-12-23
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Expires: 1998-09-29
Abstract
Abstract A line protocol format with a low bit overhead provides for the high accuracy, asynchronous exchange of digital signal information between processing units in a supervisory control system having a central processing unit (CPU) and at least one remote processing unit (RPU).
Inventors
- 👤 Richard T. Carll
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:22
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4213; H; H04; H04L; H04L5/00; H04L5/14; H04L5/16
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
240 words
A method of exchanging digital signal information asynchronously between a central processing unit (CPU) and one or remote processing units (RPU), each alternating as a sending unit and a receiving unit, comprising the steps: formatting the digital signal information at the sending unit into one or more message units, each having one or more successive serial bit cell data frames and a cyclic redundancy checking (CRC) frame, all of equal bit length, each frame including, from the least significant bit (LSB) to the most significant bit (MSB), a header field, an information field, and a trailer field, the header including a single bit (LSB) start flag and a two bit identification flag, the information field including multi-bit first and second bytes for receiving the signal information and CRC information in related frames, and the trailer field including a single bit (MSB) stop flag; encoding each message unit into a serial bi-phase signal with a signal level transistion in each bit cell of each frame, the direction of signal level transition being dependent on the binary state of the signal bit in the cell, thereby providing a manifestation of the digital signal information and time base provided by the sending unit; transmitting the bi-phase signal to the receiving unit through a transformer coupled communication line; and decoding the bi-phase signal at the receiving unit to restore the binary state of each signal bit and the time base of the sending unit.
Claim 2
Independent Claim
240 words
A method of exchanging digital signal information asynchronously between a central processing unit (CPU) and one or remote processing units (RPU), each alternating as a sending unit and a receiving unit, comprising the steps: formatting the digital signal information at the sending unit into one or more message units, each having one or more successive serial bit cell data frames and a cyclic redundancy checking (CRC) frame, all of equal bit length, each frame including, from the least significant bit (LSB) to the most significant bit (MSB), a header field, an information field, and a trailer field, the header including a single bit (LSB) start flag and a two bit identification flag, the information field including multi-bit first and second bytes for receiving the signal information and CRC information in related frames, and the trailer field including a single bit (MSB) stop flag; encoding each message unit into a serial bi-phase signal with a signal level transistion in each bit cell of each frame, the direction of signal level transition being dependent on the binary state of the signal bit in the cell, thereby providing a manifestation of the digital signal information and time base provided by the sending unit; transmitting the bi-phase signal to the receiving unit through a transformer coupled communication line; and decoding the bi-phase signal at the receiving unit to restore the binary state of each signal bit and the time base of the sending unit.
Claim 3
Dependent Claim
89 words
The method of claim 1, further including following the step of decoding, the steps of: verifying with the CRC frame the accuracy of each message unit decoded by the receiving unit; acknowledging the accuracy of each message unit decoded by the receiving unit by transmitting a serial acknowledge bi-phase encoded signal to the sending unit within a selected time interval; and monitoring, at the sending unit, the presence of said acknowledge bi-phase signal within said selected time interval, and in response to the absence thereof retransmitting the message unit.
Claim 4
Dependent Claim
123 words
The method of claim 2, wherein the step of formatting includes the steps of: addressing the RPU associated with a message unit, whether as sending unit or receiving unit, with an address signal in the first byte of the first frame information field; and identifying the first frame of each message unit transmitted by the CPU with an ID flag bit pattern different from the ID flag pattern of each successive frame in the message unit and different from the ID flag of each frame, including the first frame, of message units transmitted from each RPU, each RPU interrupting operation only in response to a message unit received with a first frame CPU ID flag pattern and first byte address identifying the RPU.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-12-23 | 1984-06-23 | 1984-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-12-23 | 1988-06-23 | 1988-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-12-23 | 1992-06-23 | 1992-12-23 | $7700.00 | Window Closed / Lapsed |