Method of fabrication of self-aligned metal-semiconductor field effect transistors

Claim 1

A method of fabricating self-aligned MESFET devices including the steps of: providing a semiconductor body having an epitaxial layer of opposite polarity deposited there on; growing of said epitaxial layer a layer of SiO 2 , said layer of SiO 2 being between about 100 A to 1000 A; depositing onto said SiO 2 layer a layer of Si 3 N 4 , said layer of Si 3 N 4 being between 200 A and 1000 A; applying a first photoresist layer on said layer of Si 3 N 4 , the thickness of the photoresist being between about 5000 A to 10,000 A; selectively exposing said first photoresist layer and developing to provide patterned opening exposing regions for sources and drains on said Si 3 N 4 layer; etching to remove said exposed Si 3 N 4 regions for sources and drains; continuing said etching to remove said SiO 2 layer beneath said exposed regions of said Si 3 N 4 exposing regions of said epitaxial layer; evaporating doped Si onto exposed regions of said epitaxial layer; lifting off said unexposed first photoresist layer leaving doped mesas for sources and drains with the area therebetween being reserved for subsequent deposition of gates; applying a second photoresist layer to said Si 3 N 4 and said doped semiconductor mesas; thickness of said second photoresist layer thickness being between about 5000 A and 10,000 A; selectively exposing said second photoresist layer and developing to expose areas of said Si 3 N 4 and said mesas while leaving intact said second photoresist layer on the Si 3 N 4 film which is over said areas reserved for said gates; removing said exposed Si 3 N 4 areas by etching; lifting off said unexposed layer of said second photoresist; oxidizing said mesas to form an oxide layer thereon of about 2000 A; etching said Si 3 N 4 film over said areas reserved for gates; etching said SiO 2 film from said region reserved for gates, exposing said epitaxial substrate; forming gates by patterning onto said exposed substrate a metal.

Claim 2

A method of fabricating self-aligned MESFET devices including the steps of: providing a semiconductor body having an epitaxial layer of opposite polarity deposited there on; growing of said epitaxial layer a layer of SiO 2 , said layer of SiO 2 being between about 100 A to 1000 A; depositing onto said SiO 2 layer a layer of Si 3 N 4 , said layer of Si 3 N 4 being between 200 A and 1000 A; applying a first photoresist layer on said layer of Si 3 N 4 , the thickness of the photoresist being between about 5000 A to 10,000 A; selectively exposing said first photoresist layer and developing to provide patterned opening exposing regions for sources and drains on said Si 3 N 4 layer; etching to remove said exposed Si 3 N 4 regions for sources and drains; continuing said etching to remove said SiO 2 layer beneath said exposed regions of said Si 3 N 4 exposing regions of said epitaxial layer; evaporating doped Si onto exposed regions of said epitaxial layer; lifting off said unexposed first photoresist layer leaving doped mesas for sources and drains with the area therebetween being reserved for subsequent deposition of gates; applying a second photoresist layer to said Si 3 N 4 and said doped semiconductor mesas; thickness of said second photoresist layer thickness being between about 5000 A and 10,000 A; selectively exposing said second photoresist layer and developing to expose areas of said Si 3 N 4 and said mesas while leaving intact said second photoresist layer on the Si 3 N 4 film which is over said areas reserved for said gates; removing said exposed Si 3 N 4 areas by etching; lifting off said unexposed layer of said second photoresist; oxidizing said mesas to form an oxide layer thereon of about 2000 A; etching said Si 3 N 4 film over said areas reserved for gates; etching said SiO 2 film from said region reserved for gates, exposing said epitaxial substrate; forming gates by patterning onto said exposed substrate a metal.