Abstract A data processing system having a system bus; a plurality of system units including a main memory, a cache memory, a central processing unit (CPU) and a communications controller all connected in parallel to the system bus. The controller operates to supervise interconnection between the units via the system bus to transfer data therebetween, and the CPU includes a memory request device for generating data requests in response to the CPU. The cache memory includes a private interface connecting the CPU to the cache memory for permitting direct transmission of data requests from the CPU to the cache memory and direct transmission of requested data from the cache memory to the CPU; a cache directory and data buffer for evaluating the data requests to determine when the requested data is not present in the cache memory; and a system bus interface connecting the cache memory to the system bus for obtaining CPU requested data not found in the cache memory from the main memory via the system bus in response to the cache directory and data buffer. The cache memory may also include replacement and update apparatus for determining when the system bus is transmitting data to be written into a specific address in main memory and for replacing the data in a corresponding specific address in the cache memory with the data then on the system bus.
A data processing system comprising: a system bus; a plurality of system units including a main memory, a cache memory, a central processing unit (CPU), and a communications controller all connected in parallel to said system bus, said controller operating to supervise interconnection between said units via said bus to transfer data therebetween and said CPU including memory request means for generating data requests; said cache memory including: private interface means connecting said cache memory directly to said CPU for permitting direct transmission of data requests from said CPU to said cache memory and direct transmission of requested data from said cache memory to said CPU; cache directory and data buffer means for evaluating said data requests and generating a first predetermined output when the requested data is not present in said cache memory; and system bus interface means connecting said cache memory to said system bus for obtaining CPU requested data not found in said cache memory from said main memory via said system bus in response to said first predetermined output from said cache directory and data buffer means.
Claim 2
Dependent Claim
181 words
A data processing system comprising: a system bus; a plurality of system units including a main memory, a cache memory, a central processing unit (CPU), and a communications controller all connected in parallel to said system bus, said controller operating to supervise interconnection between said units via said bus to transfer data therebetween and said CPU including memory request means for generating data requests; said cache memory including: private interface means connecting said cache memory directly to said CPU for permitting direct transmission of data requests from said CPU to said cache memory and direct transmission of requested data from said cache memory to said CPU; cache directory and data buffer means for evaluating said data requests and generating a first predetermined output when the requested data is not present in said cache memory; and system bus interface means connecting said cache memory to said system bus for obtaining CPU requested data not found in said cache memory from said main memory via said system bus in response to said first predetermined output from said cache directory and data buffer means.
Claim 3
Dependent Claim
44 words
The data processing system of claim 1 wherein said cache memory also includes system bus monitoring means for producing a second predetermined output when said system bus is transmitting data to be written into a specific address in said main memory from said CPU.
Claim 4
Dependent Claim
49 words
The data processing system of claim 2 wherein said cache memory also includes replacement and update means responsive to said second predetermined output for replacing data in a specific address in said cache memory corresponding to said specific address in main memory with the data on said system bus.