US4144563A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor system
Assignee: International Business Machines Corp
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Filing: 1977-11-21
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Granted: 1979-03-13
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Expires: 1997-11-21
Abstract
Abstract A single chip large scale integration processor processes its own on-chip control storage array while including the ability to also address supplemental off-chip control storage and to use such off-chip supplemental storage in substitution for portions of the on-chip storage. The processor further includes simplified arithmetic and logic (ALU) circuitry wherein the adder circuit has portions selectively gated to perform other functions with a reduced logic circuit requirement. Processor function is also enhanced by providing a read only storage (ROS) array in association with the ALU to provide multiple register loading and control functions in response to certain addresses. The processor also includes memory control circuitry that permits a group of like processors to access a single, external memory on a dynamic, prioritized basis.
Inventors
- 👤 Dale A. Heuer
- 👤 Phillip C. Schloss
- 👤 Larry L. Schroeder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 16:52
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7839; G06F15/7864
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
126 words
In a data processing system arithmetic and logic circuitry comprising an arithmetic and logic unit (ALU) having first and second input registers; said ALU having a series of bit positions equal in number to the width of the data path, each said bit position including an adder circuit, each said adder circuit including a series of gating means operable to selectively enable portions of said adder circuit; and operation decode means having a series of output gate lines each interconnected with a corresponding gating means at each of said adder bit positions, said operation decode means being operable to generate a plurality of signal combinations on said output gate lines enabling varying adder circuit portions to effect the performance of other functions by said adder circuits.
Claim 2
Dependent Claim
126 words
In a data processing system arithmetic and logic circuitry comprising an arithmetic and logic unit (ALU) having first and second input registers; said ALU having a series of bit positions equal in number to the width of the data path, each said bit position including an adder circuit, each said adder circuit including a series of gating means operable to selectively enable portions of said adder circuit; and operation decode means having a series of output gate lines each interconnected with a corresponding gating means at each of said adder bit positions, said operation decode means being operable to generate a plurality of signal combinations on said output gate lines enabling varying adder circuit portions to effect the performance of other functions by said adder circuits.
Claim 3
Dependent Claim
75 words
The data processing system arithmetic and logic circuitry of claim 1 wherein said adder circuits each comprise first and second exclusive OR circuits and a carry circuit, the inputs of the first exclusive OR circuit comprises the corresponding bit positions of said first and second input registers, and said second exclusive OR circuit has as inputs the output of said first exclusive OR circuit and the output of the carry circuit of another bit position.
Claim 4
Dependent Claim
22 words
The data processing system arithmetic and logic circuitry of claim 2 wherein said other functions include AND, OR, and exclusive OR functions.
Claim 5
Dependent Claim
201 words
The data processing system arithmetic and logic circuitry of claim 3 wherein said first exclusive OR circuit comprises first and second load devices each coupling the drain voltage to an output node, said first load device having first and second pairs of series connected field effect transistor (FET) devices interconnected between said output node and the source, the corresponding first input register bit position and a first gate line being connected respectively to the gates of said first pair of series connected FET devices, the corresponding second input register bit position and a second gate line being connected respectively to the gates of said second pair of series connected FET devices, said second load device having a third pair of series connected FET devices and a group of three series connected FET devices connected between the output node thereof and the source, said third pair of FET devices having the output node associated with said first load device and a third gate line respectively connected to the gates thereof, and said group of three series connected FET devices having the respective bit positions of said first and second input registers and a fourth gate line respectively connected to the gates thereof.
Claim 6
Dependent Claim
200 words
The data processing system arithmetic and logic circuitry of claim 4 wherein said second exclusive OR circuit comprises third and fourth load devices each coupling the drain voltage to an output node, said third load device having a first FET and a fourth pair of series connected FET devices interconnected between said output node and the source, said output node associated with said second load device and said third gate line being connected respectively to the gates of said fourth pair of series connected FET devices and the output of the carry circuit of another bit position being connected to the gate of said first FET device, said fourth load device having a second FET device connected between said output node and the source and third and fourth FET devices connected to said output node with the source sides thereof gated to the source by a fifth FET device, the gates of said second, third, fourth and fifth FET devices being respectively connected to the output node associated with said third load device, the said output of the carry circuit of said another bit position, a fifth gate line and the said output node associated with said second load device.
Claim 7
Dependent Claim
56 words
The data processing system arithmetic and logic circuitry of claim 5 wherein said carry circuit comprises an output node; a sixth FET device interconnected between said carry circuit output node and the source; and a sixth gate line connected to the gate of said sixth FET device for selectively disabling the output of said carry circuit.
Claim 8
Dependent Claim
107 words
In a data processing system arithmetic and logic circuitry comprising a first exclusive OR circuit including first and second load devices; a second exclusive OR circuit including third and fourth load devices; first and second inputs connected to said first exclusive OR circuit; third and fourth inputs connected to said second exclusive OR circuit, said third input being the output of said first exclusive OR circuit and said fourth input being a carry from a previous adder stage; and first gating means selectively operable to inhibit said fourth input, whereby the output of said second exclusive OR becomes identical to the output of said first exclusive OR.
Claim 9
Dependent Claim
107 words
In a data processing system arithmetic and logic circuitry comprising a first exclusive OR circuit including first and second load devices; a second exclusive OR circuit including third and fourth load devices; first and second inputs connected to said first exclusive OR circuit; third and fourth inputs connected to said second exclusive OR circuit, said third input being the output of said first exclusive OR circuit and said fourth input being a carry from a previous adder stage; and first gating means selectively operable to inhibit said fourth input, whereby the output of said second exclusive OR becomes identical to the output of said first exclusive OR.
Claim 10
Dependent Claim
78 words
The data processing system arithmetic and logic circuitry of claim 7 wherein said first exclusive OR includes an OR function having said first and second inputs connected to the input thereof and an AND function having said first and second inputs connected to the input thereof; and said circuitry further comprises second gating means for disabling said OR function, whereby the output of said second exclusive OR circuit becomes the output of said first exclusive OR AND function.
Claim 11
Dependent Claim
78 words
The data processing system arithmetic and logic circuitry of claim 7 wherein said first exclusive OR includes an OR function having said first and second inputs connected to the input thereof and an AND function having said first and second inputs connected to the input thereof; and said circuitry further comprises third gating means for disabling said AND function whereby the output of said second exclusive OR circuit becomes the output of said first exclusive OR OR function.
Claim 12
Dependent Claim
50 words
The data processing system arithmetic and logic circuitry of claim 9 wherein said circuitry contains a number of bit positions equivalent in number to the data path associated therewith and each such bit position includes said first and second exclusive OR circuits, and said first, second and third gating means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-12 | 1982-09-11 | 1983-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-12 | 1986-09-11 | 1987-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-12 | 1990-09-11 | 1991-03-13 | $7700.00 | Window Closed / Lapsed |