Word, byte and bit indexed addressing in a data processing system

Claim 2

A data processing system comprising: A. a data processor; B. a memory device having a plurality of locations, each said location for storing a word, each word including at least tow bytes, and each byte including a plurality of bits; C. an electrical bus coupled to transfer addressed words between said processor and said memory device, wherein said data processor includes; D. a first register for storing an unindexed address; E. a second register for storing an index value; F. a third register coupled for receiving said index value from said second register; G. transfer logic coupled to transfer said index value from said second register to said third register; H. control logic including 1. a fourth register for storing an instruction word, 2. a control storage device for storing a plurality of control store words, and 3. means, responsive to said instruction word in said fourth register, for addressing one of said control words; I. enabling means, responsive to the addressed one of said control words and said instruction word, for transferring said index value from said second register to said third register by means of said transfer logic; J. a fifth register for providing an address of a location in said memory device; and K. means, responsive to the contents of said fifth register, the contents of said third register and the unindexed address in said first register for effectively addressing a sub-portion of a said word.

Claim 3

A system as in claim 1 wherein said transfer logic includes means for shifting said index value from said second register to said third register one bit at a time.

Claim 4

A system as in claim 2 further comprising: A. means included in the contents of said fourth register for indicating whether word, byte or bit addressing is instructed; and B. means responsive to a byte instruction from said fourth register for enabling the shifting of one bit of said index value from said second register to said third register.

Claim 5

A system as in claim 3 further comprising: A. a data register, said data register including a word having a first byte and a second byte; B. indicator means included in said addressed one of said control store words for indicating both said first byte and said second byte are to be written into said memory device or whether only said first byte is to be written into said memory; C. means responsive to a first state of said indicator means for enabling both said first byte and said second byte to be written into said memory device; and D. means responsive to a second state of said indicator means for enabling only said first byte to be written into said memory device.

Claim 6

A system as in claim 4 wherein said means for enabling said first byte to be written into said memory device includes means for duplicating said first byte on said electrical bus on that portion of said bus coupled to transfer addressed words.

Claim 7

A system as in claim 5 further comprising means, responsive to the contents of said third register for indicating to said memory device that said first byte is duplicated on said electrical bus.

Claim 8

A system as in claim 3 further comprising: A. a data register for storing a word; B. means for receiving a word from said electrical bus, said word having a first byte and a second byte; and C. means, responsive to the contents of said third register, for duplicating said first byte in said data register.

Claim 9

A system as in claim 3 further comprising: A. a data register for storing a word; B. means for receiving a word from said electrical bus, said word having a first byte and a second byte; C. means, responsive to the contents of said third register, for transferring only said first byte to said data register; and D. means for transferring a masking byte having a predetermined bit pattern into that portion of said data register not occupied by said first byte.

Claim 10

A system as in claim 2 further comprising: A. a mask register; B. decoder means; C. gate means coupled to receive a decoded value from said decoder means; D. means included in the contents of said fourth register for indicating whether word, byte or bit addressing is instructed; E. means responsive to a bit instruction from said fourth register for enabling the shifting of four contiguous bits from said second register to said third register; F. means responsive to the addressed one of said control store words for enabling the decoding of said four bits in said third register to produce a said decoded value of word length with a first state in one bit position thereof and a second state in each of the other bit positions thereof; and G. means, including said gate means, responsive to said addressed one of said control store words, for transferring said decoded value to said mask register.

Claim 11

A system as in claim 9 further comprising means for operating on only that bit in the corresponding position of said first state of said decoded value in said mark register of the word in said memory device addressed by means of said fifth register.

Claim 12

A data processing system comprising: A. a memory device having a plurality of locations for storing words, said words including at least two bytes, said bytes including a plurality of bits; B. a base register for storing an unindexed address of a said location in said memory device; C. an index register for storing an index value, said index value having a word index portion, a byte index portion and a bit index portion, said byte index portion included in said bit index portion; D. an instruction register having an instruction word, said instruction word including a first field for indicating an operation code which in turn indicates whether full word or byte or bit addressing of a location in said memory device is to be performed, said instruction word further comprising a second field for indicating whether said index value is to be used in modifying the unindexed address; E. logic means, responsive to said first field and said second field in said instruction word contained in said instruction register, for addressing a said location in said memory device based on said unindexed address plus the value of said word index portion, said location hereinafter referred to as said addressed word location; F. means, responsive to said byte index portion in said index register, for addressing one of said bytes in said addressed word location if said first field in said instruction word indicates that byte addressing is to be performed; and G. means, responsive to said bit index portion in said index register, for addressing one of said bits in said addressed word location if said first field in said instruction word indicates that bit addressing is to be performed.

Claim 13

A data processing system comprising: A. a memory device having a plurality of locations for storing words, said words including at least two bytes, said bytes including a plurality of bits; B. a base register for storing an unindexed address of a said location in said memory device; C. an index register for storing an index value, said index value having a word index portion, a byte index portion and a bit index portion, said byte index portion included in said bit index portion; D. an instruction register having an instruction word, said instruction word including a first field for indicating an operation code which in turn indicates whether full word or byte or bit addressing of a location in said memory device is to be performed, said instruction word further comprising a second field for indicating whether said index value is to be used in modifying the unindexed address; E. logic means, responsive to said first field and said second field in said instruction word contained in said instruction register, for addressing a said location in said memory device based on said unindexed address plus the value of said word index portion, said location hereinafter referred to as said addressed word location; F. means, responsive to said byte index portion in said index register, for addressing one of said bytes in said addressed word location if said first field in said instruction word indicates that byte addressing is to be performed; and G. means, responsive to said bit index portion in said index register, for addressing one of said bits in said addressed word location if said first field in said instruction word indicates that bit addressing is to be performed.

Claim 14

A system as in claim 11 wherein said logic means comprises: A. a control storage device having a plurality of control store words therein, each of said control store words having a plurality of fields, each of said fields for indicating the manner in which said system is to be coupled for operation; B. means, responsive to said instruction word, for addressing one of said control store words; C. means, responsive to said addressed control store word, for enabling said byte and bit addressing.