Apparatus for altering computer memory by bit, byte or word

Claim 2

Data processing apparatus comprising A. a memory having a plurality of word storage locations, where a word includes a plurality of bytes and a byte is composed of a plurality of bits such that there are N bits in a word; B. a data register adapted to store a data word; C. buffer means adapted to receive a data quantity of bit, byte or word size; D. means for addressing a memory word storage location; E. N transfer leads for loading the data word stored at said addressed location in said register; F. means responsive to each received data quantity to produce bit, byte or word control signals according to the size of the received quantity corresponding to the position thereof in a data word; and G. means for altering said loaded data word including a gating network selectively enabled by said control signals to route the received data quantities from said buffer means to their corresponding positions of said loaded data word without altering any bit positions which remain.

Claim 3

Apparatus as set forth in claim 1 wherein said buffer means includes at least one single bit buffer for receiving serial sequences of bits, at least one byte buffer for receiving bytes and at least one word buffer or receiving words, said bit, byte and word sized data being received via sepaRate data channels.

Claim 4

producing a first byte location signal when the counter has counted enough bits to constitute a byte, and

Claim 5

producing a first byte location signal when the counter has counted enough bits to constitute a byte, and

Claim 6

responsive to said received byte, for generating a byte control signal indicative of the position of said byte in said loaded word; B. means, connected to said byte buffer, for placing said received byte on said data lines; and C. wherein said gating means is selectively enabled by said byte control signal to transfer said received byte from said data lines to a corresponding byte location of said loaded word.

Claim 7

responsive to said received byte, for generating a byte control signal indicative of the position of said byte in said loaded word; B. means, connected to said byte buffer, for placing said received byte on said data lines; and C. wherein said gating means is selectively enabled by said byte control signal to transfer said received byte from said data lines to a corresponding byte location of said loaded word.

Claim 8

alternately, producing a second byte location signal every other time that the counter has counted enough bits to constitute a byte; and wherein said control signal producing means is coupled to said decoder so as to generate said bit control signal indicative of the position of the received bit.

Claim 9

alternately, producing a second byte location signal every other time that the counter has counted enough bits to constitute a byte; and wherein said control signal producing means is coupled to said decoder so as to generate said bit control signal indicative of the position of the received bit.

Claim 10

Apparatus as set forth in claim 2 wherein said altering means includes A. N data lines apportioned into at least first and second byte groups; B. means coupled to said single bit buffer for assembling a received bit on each of the bit lines of said first byte group; C. means coupled to said first byte group lines and conditioned by the absence of a word size control signal for assembling said received bit on all of said second byte group lines; and D. means coupling said N data lines to separate bit locations of said register.

Claim 11

The invention according to claim 3 wherein said data assembling means further includes: A. means coupled to said byte buffer for transferring a received byte to the bit lines of said first byte group; and B. means coupled to said first byte group lines and conditioned by the absence of a word size control signal for assembling the bits of said received byte on to said second byte group lines wherein said received byte appears on each of said first and second byte group lines.

Claim 12

The invention according to claim 4 wherein said data assembly means further includes: A. means coupled to said word buffer for transferring a first byte of a received word to said first byte group lines; B. means coupled to said word buffer for transferring a second byte of a received word to a third group of bit lines; C. means coupling said third group of lines to said second byte group of lines when conditioned by the presence of a word size control signal.

Claim 13

Data processing apparatus as set forth in claim 3 wherein said means for producing control signals includes: A. a counter coupled to said single bit buffer for counting each bit in a received serial sequence; B. a decoder coupled to said counter for

Claim 14

Data processing apparatus as defined in claim 6 wherein said data assembling means further includes; A. means coupled to said byte buffer for transferring a received byte to the bit lines of said first byte group; and B. means coupled to said first byte group lines and conditioned by the absence of a word size control signal for assembling the bits of said received byte on to said second byte group lines wherein said received byte appears on each of said first and second byte group lines.

Claim 15

The invention as defined in claim 7 wherein said data assembly means further includes: A. means coupled to said word buffer for transferring a first byte of a received word to said first byte group lines; B. means coupled to said word buffer for transferring a second byte of a received word to a third group of bit lines; C. means coupling said third group of lines to said second byte group of lines when conditioned by the presence of a word size control signal.

Claim 16

Data processing apparatus, comprising A. a memory having a plurality of word storage locations, where a word includes a plurality of bytes and a byte is composed of a plurality of bits such that there are N bits in a word; B. a data register adapted to store a data word; C. a bit buffer for receiving a serial sequence of bits; D. means for addressing a memory word storage location; E. N transfer leads for loading the data word stored at said addressed location in said register; F. means responsive to each received bit for generating a bit control signal corresponding to the position of each received bit in a data wOrd; G. N data lines and means coupled to said bit buffer for placing each received bit on all of said data lines; and H. means for altering said loaded word including gating means selectively enabled by each bit control signal to transfer each received bit to the corresponding bit position of said loaded word from a corresponding one of said data lines without altering the remainder of said loaded word.

Claim 17

Data processing apparatus, comprising A. a memory having a plurality of word storage locations, where a word includes a plurality of bytes and a byte is composed of a plurality of bits such that there are N bits in a word; B. a data register adapted to store a data word; C. a bit buffer for receiving a serial sequence of bits; D. means for addressing a memory word storage location; E. N transfer leads for loading the data word stored at said addressed location in said register; F. means responsive to each received bit for generating a bit control signal corresponding to the position of each received bit in a data wOrd; G. N data lines and means coupled to said bit buffer for placing each received bit on all of said data lines; and H. means for altering said loaded word including gating means selectively enabled by each bit control signal to transfer each received bit to the corresponding bit position of said loaded word from a corresponding one of said data lines without altering the remainder of said loaded word.

Claim 18

A system as defined in claim 9 wherein the remaining bits of said loaded word are unaltered by said gating means.

Claim 19

A system as defined in claim 10 wherein said generating means includes: A. means, coupled to said bit buffer for sequentially counting the received bits; B. means for detecting the receipt of a plurality of bits, said 5 plurality of bits forming a byte, and generating a byte location signal indicative of the byte location in said loaded word; and C. means for gating said byte location signal and the count of said counting means to produce said bit control signal indicative of the bit position of said received bit.

Claim 20

A data processing system as defined in claim 11 wherein said counting means is recycled after each byte is received.

Claim 21

A data processing system as defined in claim 11 further including: A. at least one byte buffer

Claim 22

A data processing system as defined in claim 11 further including: A. at least one word buffer adapted to receive a word of data; B. means, responsive to said received word, for generating a word control signal; C. means, connected to said word buffer, for placing said received word on said data lines; and D. wherein said gating means responds to the absence of bit and byte control signals to load said received word into said data register.