US4065808A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Network computer system
Assignee: US Philips Corp
•
Filing: 1976-01-15
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Granted: 1977-12-27
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Expires: 1996-01-15
Abstract
Abstract A network computer system in which the individual processors are arranged in the form of a matrix, with each processor connected with its directly neighboring processors. The individual processors are checkerboard-like assigned to one of two groups, and each group is connected, by its own instruction line, to a control unit for connection to the control computer. The system is useful in performing iterative calculations in which the processors of the one group calculate new values on the basis of initial data previously calculated by the directly adjacent respective processors of the other group.
Inventors
- 👤 Hermann Schomberg
- 👤 Frank Heubach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:21
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8023; G06F17/00; G06F17/10; G06F17/11; G06F17/13
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
124 words
A multiprocessor computer system comprising: a control computer and a control unit connected thereto; first and second groups of identical processors arranged in a matrix array, each of said processors of one group lying directly adjacent to at least two of said processors of the other group and connected to said adjacent processors by means of data exchange lines; each group of said processors being separately connected to said control unit by instruction lines and signalling lines for transmitting non-corresponding instructions from said control computer to each group of processors; and a buffer store connected to said control unit by data lines and connected to at least some of said processors for storing information for processing by said at least some of said processors.
Claim 2
Dependent Claim
124 words
A multiprocessor computer system comprising: a control computer and a control unit connected thereto; first and second groups of identical processors arranged in a matrix array, each of said processors of one group lying directly adjacent to at least two of said processors of the other group and connected to said adjacent processors by means of data exchange lines; each group of said processors being separately connected to said control unit by instruction lines and signalling lines for transmitting non-corresponding instructions from said control computer to each group of processors; and a buffer store connected to said control unit by data lines and connected to at least some of said processors for storing information for processing by said at least some of said processors.
Claim 3
Dependent Claim
54 words
A computer system as claimed in claim 1, wherein said control unit is connected between said control computer and said processors, said control unit comprising a program store and two instruction decoders connected to said program store, each of said decoders feeding said instruction lines for an individual one of said groups of processors.
Claim 4
Dependent Claim
34 words
A computer system as claimed in claim 2, wherein said control unit comprises a switching matrix controlled by said decoders for controlling the data and instruction paths between the control computer and said processors.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-12-26 | 1981-06-27 | 1981-12-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-12-26 | 1985-06-27 | 1985-12-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-12-26 | 1989-06-27 | 1989-12-27 | $7700.00 | Window Closed / Lapsed |