US4058711A
Expired / Lapsed
US
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Asynchronous dual function multiprocessor machine control
Assignee: Milacron Inc
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Filing: 1976-04-16
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Granted: 1977-11-15
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Expires: 1996-04-16
Abstract
Abstract A multiprocessor system is disclosed for controlling a cycle of operation of a machine. The cycle of operation of the machine is governed by a first set of devices and is monitored by a second set of devices. The multiprocessor system includes a logic processor unit containing a first program of logic instructions defining the cycle of operation of the machine. A bus and associated circuits are connected between the logic processor and the devices on the machine. The logic processor is responsive to the second set of devices and makes logic decisions in a continuous and cyclic manner to control the operation of the first devices thereby causing the cycle of operation of the machine to conform with the first program. The multiprocessor system further includes one or more independent data processors which are connected to the bus and operate asynchronously with the logic processor. The data processors respond to output signals from the logic processor which select preprogrammed sets of arithmetic instructions. The data processors execute the selected sets of arithmetic instructions and produce control signals which are accepted by the logic processor at the appropriate time in its own cycle of operation.
Inventors
- 👤 Robert Michael Ondercin
- 👤 Paul Stephen Borzcik
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 23:44
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G05B19/052; G05B2219/00; G05B2219/10; G05B2219/11; G05B2219/1105; G05B2219/1125; G05B2219/1159; G05B2219/13; G05B2219/13004; G05B2219/13017; G05B2219/13092; G05B2219/13128; G05B2219/13159; G05B2219/14; G05B2219/14144; G05B2219/15; G05B2219/15018; G05B2219/15055; G05B2219/15081; G05B2219/15127
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
163 words
An apparatus for controlling a machine, said machine having input devices generating input signals in response to the machine operation and further having output devices for receiving output signals to modify the machine operation, the apparatus comprising: a. a single data bit contact bus; b. means connected between the contact bus and the devices on the machine for interfacing the input and output signals between the contact bus and the input and output devices, respectively; c. a single data bit logic processor means connected to the contact bus and reponsive to the input signals for generating the output signals in response to the machine operating in accordance with a stored set of logic instructions; d. a data processor means connected to the contact bus for producing a further input signal by executing asynchronously with the logic processor means a stored set of arithmetic instructions in response to one of the output signals; and e. data communication means connected to the data processor means.
Claim 2
Independent Claim
163 words
An apparatus for controlling a machine, said machine having input devices generating input signals in response to the machine operation and further having output devices for receiving output signals to modify the machine operation, the apparatus comprising: a. a single data bit contact bus; b. means connected between the contact bus and the devices on the machine for interfacing the input and output signals between the contact bus and the input and output devices, respectively; c. a single data bit logic processor means connected to the contact bus and reponsive to the input signals for generating the output signals in response to the machine operating in accordance with a stored set of logic instructions; d. a data processor means connected to the contact bus for producing a further input signal by executing asynchronously with the logic processor means a stored set of arithmetic instructions in response to one of the output signals; and e. data communication means connected to the data processor means.
Claim 3
Independent Claim
133 words
An apparatus for controlling a machine having input devices for generating input signals representing the actual electrical states of the input devices in response to the machine operation and further having output devices for receiving output signals commanding the electrical state of the output devices to modify the machine operation, the apparatus comprising: a. a single data bit contact bus; b. means connected to the contact bus and the devices on the machine for interfacing the input and output signals between the contact bus and the input and output devices respectively; c. a single data bit logic processor means connected to the contact bus and including 1. means for storing logic instructions representing a pattern of predetermined states of the input signals thereby defining a desired cycle of operation of the machine, and
Claim 4
Independent Claim
133 words
An apparatus for controlling a machine having input devices for generating input signals representing the actual electrical states of the input devices in response to the machine operation and further having output devices for receiving output signals commanding the electrical state of the output devices to modify the machine operation, the apparatus comprising: a. a single data bit contact bus; b. means connected to the contact bus and the devices on the machine for interfacing the input and output signals between the contact bus and the input and output devices respectively; c. a single data bit logic processor means connected to the contact bus and including 1. means for storing logic instructions representing a pattern of predetermined states of the input signals thereby defining a desired cycle of operation of the machine, and
Claim 5
Dependent Claim
144 words
means responsive to the storing means and connected to the contact bus for producing the output signals in response to the actual states of the devices on the machine corresponding to the predetermined states of said devices; d. a data processor means connected to the contact bus and operating asynchronously with the logic processor means, said data processor means including 1. means responsive to one of the output signals for selecting a stored program of arithmetic instructions, 2. data storage for storing data signals, and 3. means responsive to the selecting means and the data signals for executing the arithmetic instructions to cause a further input signal to be available on the contact bus for use by said logic processor means; and e. data communication means connected to the data processor means for transferring the data signals to and from the data processor means.
Claim 6
Dependent Claim
144 words
means responsive to the storing means and connected to the contact bus for producing the output signals in response to the actual states of the devices on the machine corresponding to the predetermined states of said devices; d. a data processor means connected to the contact bus and operating asynchronously with the logic processor means, said data processor means including 1. means responsive to one of the output signals for selecting a stored program of arithmetic instructions, 2. data storage for storing data signals, and 3. means responsive to the selecting means and the data signals for executing the arithmetic instructions to cause a further input signal to be available on the contact bus for use by said logic processor means; and e. data communication means connected to the data processor means for transferring the data signals to and from the data processor means.
Claim 7
Independent Claim
265 words
An apparatus for controlling a machine having input devices for generating single bit input signals representing the actual electrical states of the input devices in response to the machine operation, output devices for receiving single bit output signals commanding the electrical state of the output devices to modify the machine operation, and other devices for generating multiple bit data signals, the apparatus comprising: a. a single data bit contact bus; b. means connected to the contact bus and the input and output devices for interfacing the input and output signals therebetween; c. a single data bit logic processor means connected to the contact bus and including 1. means for storing logic instructions representing a pattern of predetermined states of the input and output devices thereby defining a desired cycle of operation of the machine, and 2. means responsive to the storing means and connected to the contact bus for producing the output signals in response to the actual states of the devices on the machine corresponding to the predetermined states of said devices; d. a multiple bit data bus; e. means connected to the data bus and the other devices for interfacing the data signals therebetween; f. a plurality of multiple bit data processor means connected to the contact bus and the data bus and operating asynchronously with the logic processor means, each of the data processor means including 1. means connected to the data bus and the data processor means for transferring the data signals threbetween, 2. means responsive to one of the output signals for selecting a stored program of arithmetic instructions, and
Claim 8
Independent Claim
265 words
An apparatus for controlling a machine having input devices for generating single bit input signals representing the actual electrical states of the input devices in response to the machine operation, output devices for receiving single bit output signals commanding the electrical state of the output devices to modify the machine operation, and other devices for generating multiple bit data signals, the apparatus comprising: a. a single data bit contact bus; b. means connected to the contact bus and the input and output devices for interfacing the input and output signals therebetween; c. a single data bit logic processor means connected to the contact bus and including 1. means for storing logic instructions representing a pattern of predetermined states of the input and output devices thereby defining a desired cycle of operation of the machine, and 2. means responsive to the storing means and connected to the contact bus for producing the output signals in response to the actual states of the devices on the machine corresponding to the predetermined states of said devices; d. a multiple bit data bus; e. means connected to the data bus and the other devices for interfacing the data signals therebetween; f. a plurality of multiple bit data processor means connected to the contact bus and the data bus and operating asynchronously with the logic processor means, each of the data processor means including 1. means connected to the data bus and the data processor means for transferring the data signals threbetween, 2. means responsive to one of the output signals for selecting a stored program of arithmetic instructions, and
Claim 9
Dependent Claim
35 words
means responsive to the selecting means and the data signals for executing the arithmetic instructions to cause a further input signal to be available on the contact bus for use by said logic processor means.
Claim 10
Dependent Claim
35 words
means responsive to the selecting means and the data signals for executing the arithmetic instructions to cause a further input signal to be available on the contact bus for use by said logic processor means.
Claim 11
Dependent Claim
37 words
The apparatus of claim 3, wherein the apparatus further comprises a bulk data store connected to the data bus whereby data signals may be transferred from the bulk data store to any of the data processor means.
Claim 12
Dependent Claim
39 words
The apparatus of claim 3, wherein each of the data processor means further comprises a data store for receiving and storing data signals from the transferring means whereby said data signals may be subsequently used by the executing means.
Claim 13
Independent Claim
159 words
An apparatus for controlling the operation of a machine, said machine having input devices for generating single bit input signals representing the actual electrical states of the input devices and output devices for operating the machine in response to single bit output signals commanding the electrical states of the input devices, the apparatus comprising: a. a single data bit contact bus; b. means connected to the contact bus and the input and output devices for interfacing the input and output signals therebetween; c. a single data bit logic processor means connected to the contact bus and including 1. a memory for storing a series of memory words representing the desired states and device addresses of the input and output devices and logic instructions associated therewith, thereby simulating the desired cycle of operation of the machine, 2. means for continuously reading the memory words in an iterative fixed sequential cycle to provide the device addresses on the contact bus, and
Claim 14
Independent Claim
159 words
An apparatus for controlling the operation of a machine, said machine having input devices for generating single bit input signals representing the actual electrical states of the input devices and output devices for operating the machine in response to single bit output signals commanding the electrical states of the input devices, the apparatus comprising: a. a single data bit contact bus; b. means connected to the contact bus and the input and output devices for interfacing the input and output signals therebetween; c. a single data bit logic processor means connected to the contact bus and including 1. a memory for storing a series of memory words representing the desired states and device addresses of the input and output devices and logic instructions associated therewith, thereby simulating the desired cycle of operation of the machine, 2. means for continuously reading the memory words in an iterative fixed sequential cycle to provide the device addresses on the contact bus, and
Claim 15
Dependent Claim
217 words
means connected between the memory and the contact bus for generating the output signals in response to the actual operating conditions on the machine as represented by the input signals corresponding to the desired operating conditions on the machine as represented by the memory words; d. a data processor means connected to the contact bus and operating asynchronously with the logic processor means, said data processor means including 1. a program store for storing a number of macroinstruction programs each containing a series of arithmetic instructions, 2. means connected between the contact bus and the program store for selecting one of the programs in response to one of the output signals, 3. means responsive to the program store for decoding each macroinstruction ot produce a number of microinstructions and timing signals, 4. a data store for storing a number of data signals, and 5. means connected to the data store and the decoding means for executing the microinstructions to generate a control signal to the selecting means thereby causing the data processor means to transmit a further input signal to the contact bus in response to a device address corresponding to the further input signal; and e. data communication means connected to the data processor for transferring the data signals to and from the data communication means.
Claim 16
Dependent Claim
217 words
means connected between the memory and the contact bus for generating the output signals in response to the actual operating conditions on the machine as represented by the input signals corresponding to the desired operating conditions on the machine as represented by the memory words; d. a data processor means connected to the contact bus and operating asynchronously with the logic processor means, said data processor means including 1. a program store for storing a number of macroinstruction programs each containing a series of arithmetic instructions, 2. means connected between the contact bus and the program store for selecting one of the programs in response to one of the output signals, 3. means responsive to the program store for decoding each macroinstruction ot produce a number of microinstructions and timing signals, 4. a data store for storing a number of data signals, and 5. means connected to the data store and the decoding means for executing the microinstructions to generate a control signal to the selecting means thereby causing the data processor means to transmit a further input signal to the contact bus in response to a device address corresponding to the further input signal; and e. data communication means connected to the data processor for transferring the data signals to and from the data communication means.
Claim 17
Dependent Claim
142 words
The apparatus of claim 6, wherein the means for generating the output signals further comprises: a. means for decoding the memory words to produce input, output and OR element signals, said input and output element signals having device address signals associated therewith; b. means serially responsive to consecutive memory words having input element signals and first device addresses for comparing desire machine condition as defined by the consecutive memory words with the actual machine conditions as defined by the input signals associated with the first device addresses; and c. means responsive to the decoding and the comparing means for providing an output signal in response to a continuous correspondence between the desired and actual machine conditions and the subsequent decoding of OR element signal or an output element signal, whereby said comparing and providing means operate to execute a logical AND function.
Claim 18
Dependent Claim
135 words
The apparatus of claim 7, wherein the means for providing the output signal further comprises: a. first storage means connected to the comparing means and responsive to the decoding of successive memory words for storing a first signal in response to a continuous correspondence between the desired and actual machine conditions; b. second storage means connected to the first storage means and the decoding means for storing the first signal and reseting the first storage means in response to an OR element signal; and c. means responsive to the first and second storage means, and the decoding means for producing the output signal in response to the first signal and the beginning of an output element signal and resetting the first and second storage means in response to the end of the output element signal.
Claim 19
Dependent Claim
64 words
the apparatus of claim 8, wherein said machine further includes other devices for generating and receiving data signals and the data communication means further comprises: a. a data bus; b. means connected to the data bus and the other devices for interfacing the data signals therebetween; and c. means connected between the data bus and the data processor means for multiplexing the signals therebetween.
Claim 20
Dependent Claim
17 words
The apparatus of claim 9, wherein the memory is comprised of a nonvolatile electrically alterable readonly memory.
Claim 21
Dependent Claim
62 words
The apparatus of claim 10, wherein the selecting means further comprises: a. means responsive to the one of the output signals and second device addresses for decoding and storing said second device address; and b. a program counter responsive to the stored second device address for setting a predetermined number therein thereby selecting the one of the macroprograms in the program store.
Claim 22
Dependent Claim
26 words
The apparatus of claim 11, wherein the data signals represent binary coded decimal numbers and the data store further comprises a binary coded decimal storage circuit.
Claim 23
Dependent Claim
55 words
The apparatus of claim 12, wherein the executing means further comprises an arithmetic unit responsive to the binary coded decimal numbers for executing each of said macroinstructions by means of a fixed cycle comprised of a predetermined fixed number of passes through the arithmetic unit with a predetermined fixed number of timing counts per pass.
Claim 24
Independent Claim
343 words
An apparatus for controlling a machine having input devices for generating input signals representing the actual electrical states of the input devices in response to the operation of the machine, output devices for receiving output signals commanding the actual electrical states of the output devices to control the operation of the machine, and other devices for generating and receiving data signals, the apparatus comprising: a. a single data bit contact bus; b. an interface circuit connected between the contact bus and the input and output devices for controlling the communication of the input and output signals between the contact bus and said input and output devices; c. a logic processor including 1. a logic program storage circuit containing memory words defining a predetermined pattern of desired conditions of the input and output devices and associated device addresses, and 2. means responsive to the logic program storage circuit and the contact bus for producing the output signals in response to the actual conditions on the machine as represented by the input signals corresponding to the desired conditions as represented by the memory words; d. a data bus; e. a data interface circuit connected between the data bus and the other devices for controlling the communication of data signals between the data bus and the other devices; f. a data processor operating asynchronously with said logic processor and including 1. a multiplexing circuit connected between the data bus and the data processor for multiplexing the data signals between the data bus and the data processor, 2. a data store responsive to the multiplexing circuit for storing data signals, 3. a macroinstruction program store responsive to the contact bus for providing a set of arithmetic instructions in response to one of the output signals and a corresponding device address; and 4. an arithmetic unit responsive to the data store, the multiplexing circuit and the program store for executing the set of arithmetic instructions using the data signals to cause a further input signal to be provided on the contact bus in response to corresponding device address.
Claim 25
Independent Claim
343 words
An apparatus for controlling a machine having input devices for generating input signals representing the actual electrical states of the input devices in response to the operation of the machine, output devices for receiving output signals commanding the actual electrical states of the output devices to control the operation of the machine, and other devices for generating and receiving data signals, the apparatus comprising: a. a single data bit contact bus; b. an interface circuit connected between the contact bus and the input and output devices for controlling the communication of the input and output signals between the contact bus and said input and output devices; c. a logic processor including 1. a logic program storage circuit containing memory words defining a predetermined pattern of desired conditions of the input and output devices and associated device addresses, and 2. means responsive to the logic program storage circuit and the contact bus for producing the output signals in response to the actual conditions on the machine as represented by the input signals corresponding to the desired conditions as represented by the memory words; d. a data bus; e. a data interface circuit connected between the data bus and the other devices for controlling the communication of data signals between the data bus and the other devices; f. a data processor operating asynchronously with said logic processor and including 1. a multiplexing circuit connected between the data bus and the data processor for multiplexing the data signals between the data bus and the data processor, 2. a data store responsive to the multiplexing circuit for storing data signals, 3. a macroinstruction program store responsive to the contact bus for providing a set of arithmetic instructions in response to one of the output signals and a corresponding device address; and 4. an arithmetic unit responsive to the data store, the multiplexing circuit and the program store for executing the set of arithmetic instructions using the data signals to cause a further input signal to be provided on the contact bus in response to corresponding device address.
Claim 26
Dependent Claim
84 words
The apparatus of claim 2, wherein said machine further includes other devices for generating the data signals and the data communication means further comprises: a. a data bus for conducting the data signals; b. means connected between the other devices and the data bus for interfacing the data signals from the other devices to the data bus; and c. means connected between the data bus and the data processor means for transferring the data signals from the data bus to the data processor means.
Claim 27
Dependent Claim
65 words
The apparatus of claim 13, wherein the apparatus further comprises an intercommuncation circuit connected between the contact the data buses for converting 1. single data bit output signals from the logic processor means into multiple bit data signals for the data processor means, and 2. multiple bit data signals from the data processor means into single data bit input signals for the logic processor means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-11-14 | 1981-05-16 | 1981-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-11-14 | 1985-05-16 | 1985-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-11-14 | 1989-05-16 | 1989-11-15 | $7700.00 | Window Closed / Lapsed |