US3731280A
Expired / Lapsed
US
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Programmable controller
Assignee: Varisystems Corp
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Filing: 1972-03-16
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Granted: 1973-05-01
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Expires: 1992-03-16
Abstract
Abstract A programmable controller for use in controlling a wide variety of external data and production devices and having an extremely flexible stored program capability enabling the device to function as a small-scale computer adapted for use as either a systems controller or as a ''''stand alone'''' mini-computer.
Inventors
- 👤 R Shevlin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:06
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/042; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F40/00; G06F40/10; G06F40/189
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
272 words
A controller comprising: a clock source; instruction sequencer means for sequentially controlling a plurality of controller operations; program counting means for counting program steps, said program counting means including means for storing program steps; instruction register means for storing an instruction word; decoder means for decoding the operation called for in the instruction stored in said instruction register; said sequencer means including a plurality of shift registers each storing a group of sequentially controlled signals; means coupling said decoder means to a selected one of said sequencer registers dependent upon the operation called for by the instruction in said instruction register; said clock means being coupled to said sequencer means for sequentially shifting out the sequential control signals from the selected register; accumulator means; memory means; input-output control means for coupling data from peripheral circuitry to said controller; common bus means having input means coupled to the outputs of said instruction register, said program counter and said memory means; said accumulator means and said input-output control means; said common bus means including output means and multiplexer means for selecting the input to be passed to the output means of said common bus; means coupling said instruction sequencer to said common bus means multiplexer for selecting the input to be passed by the output of said common bus means; means coupled to said instruction sequencer means for selectively coupling the output of said common bus means to one of said memory means, said accumulator means, said instruction register means, program counter means; said accumulator means and said input-output control means selectively in accordance with the sequential control signal developed by said sequencer means.
Claim 2
Dependent Claim
272 words
A controller comprising: a clock source; instruction sequencer means for sequentially controlling a plurality of controller operations; program counting means for counting program steps, said program counting means including means for storing program steps; instruction register means for storing an instruction word; decoder means for decoding the operation called for in the instruction stored in said instruction register; said sequencer means including a plurality of shift registers each storing a group of sequentially controlled signals; means coupling said decoder means to a selected one of said sequencer registers dependent upon the operation called for by the instruction in said instruction register; said clock means being coupled to said sequencer means for sequentially shifting out the sequential control signals from the selected register; accumulator means; memory means; input-output control means for coupling data from peripheral circuitry to said controller; common bus means having input means coupled to the outputs of said instruction register, said program counter and said memory means; said accumulator means and said input-output control means; said common bus means including output means and multiplexer means for selecting the input to be passed to the output means of said common bus; means coupling said instruction sequencer to said common bus means multiplexer for selecting the input to be passed by the output of said common bus means; means coupled to said instruction sequencer means for selectively coupling the output of said common bus means to one of said memory means, said accumulator means, said instruction register means, program counter means; said accumulator means and said input-output control means selectively in accordance with the sequential control signal developed by said sequencer means.
Claim 3
Dependent Claim
54 words
The controller of claim 1 wherein said instruction sequencer further comprises a fetch register for sequentially developing a plurality of fetch signals when actuated to cause the next program step to be performed; means coupled to the last control signals of selected ones of said sequencer means shift registers for actuating said fetch register.
Claim 4
Dependent Claim
22 words
The controller of claim 2 wherein said input-output control means comprises means coupled to said sequencer means for operating said peripheral circuits.
Claim 5
Dependent Claim
121 words
The controller of claim 2 further comprising: display means means for displaying output information coupled to said input-output control means; printer means including keyboard means coupled to said input-output control means; external data source means coupled to said input-output control means; output recording means coupled to said input-output control means; said input-output control means including means coupled to said sequencer means for transferring the output of said common bus means to one of said printer means, output recording means or display means; said input-output control means further comprising means coupled to said sequencer means selectively coupling one of said external data source means and said printer keyboard means to said common bus for entering data to be converted into said controller.
Claim 6
Dependent Claim
99 words
The controller of claim 4 wherein said keyboard means is adapted to insert characters and other symbols into said controller in binary form; said accumulator means bEing responsive to data from said external data source and said character information for determining the amount of characters which can be accommodated in a line of print; said display means comprising means for displaying the space remaining in the line of print being entered; said recording means being adapted to print an output representing the spacing and positioning of the characters in each line of print for use in controlling a justifier.
Claim 7
Dependent Claim
137 words
The controller of claim 1 further comprising means for scanning an image; means for converting each scanned point of said image into signals each representing one of two binary states; means coupling said converting means to said input-output control means for sequentially entering said signals into said accumulator in groups, each group containing a plurality of said signals; means coupled between said sequencer means and said accumulator means for counting the number of consecutive signals of the same binary state; means coupled to said accumulator means for terminating said count when the next consecutive signal is of the opposite state to start a new count; means coupled between said accumulator and said input-output control means for outputting each completed count in the form of binary signal groups to said input-output means for transmission to a remote location.
Claim 8
Dependent Claim
79 words
The controller of claim 6 further comprising means for receiving the binary signal groups representing said counts; second controller means including means coupled to said receiving means for converting said signal groups into binary signals representing the original form of said binary signals representing said image prints; means coupled to said second controller means for generating a line whose contrast values are determined by the state of the binary signals representing the image points scanned by said scanning means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-30 | 1976-10-30 | 1977-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-30 | 1980-10-30 | 1981-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-30 | 1984-10-30 | 1985-05-01 | $7700.00 | Window Closed / Lapsed |