US4053950A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Residual status reporting during chained cycle steal input/output operations
Assignee: International Business Machines Corp
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Filing: 1976-04-30
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Granted: 1977-10-11
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Expires: 1996-04-30
Abstract
Abstract A data processing system with improved input/output (I/O) techniques is disclosed. The input/output control logic, or channel, of a central processing unit is connected to a plurality of peripheral input/output device control units, in parallel, by a plural line interface bus which includes bidirectional data transfer lines and bidirectional address transfer wires. The interface bus also includes unidirectional lines to and from peripheral device control units which synchronize operation of use of the bus. Several forms of I/O communications are shown to be controlled by the interface bus and include, direct processor controlled data transfer with simultaneous transmission of data and commands to peripheral devices, cycle steal data transfers permitting concurrent input/output operations and central processor program instruction execution, and peripheral device initiated interrupt requests to the central processor. A common polling mechanism for selecting one of a plurality of peripheral devices which may be requesting cycle steal use of the bus or interrupt handling use of the bus is disclosed. During cycle steal data transfers, peripheral device status information can be transferred over the interface bus to the central processor storage without the need for requesting interrupt handling from the central processor.
Inventors
- 👤 Donall Garraid Bourke
- 👤 Louis Peter Vergari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:08
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/32; G06F13/34
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
330 words
A data processing system comprising: central storage means for data, program instructions, including operate I/O instructions, and peripheral device control blocks comprised of a plurality of control fields, a peripheral device control unit including peripheral storage means for a peripheral device control block, input/output interface logic including a data bus, address bus, and control signal lines interconnecting said central storage and peripheral device control unit, a central processor connected to said central storage and said input/output interface logic, responsive to each said operate I/O instruction for initiating operation of said central storage and said interface logic for transferring to said peripheral device control unit a peripheral device control block, said peripheral device control block including in the control fields, a first field comprised of a plurality of control bits, a central storage data address field specifying a data field in central storage involved in the data transfer, a count field specifying the amount of data to be transferred, and a chained device control block address field specifying the central storage location of a succeeding device control block to be transferred after use of the current device control block; said peripheral device control unit including, device control block access means connected to said input/output interface logic, responsive to a predetermined state of one of said control bits and first signalling means indicating normal completion of use of the current device control block to access from said central storage the next succeeding device control block, interrupt requesting means connected to said input/output interface logic, responsive to a second signalling means indicating unusual completion of use of the current device control block to signal an interrupt request to said central processor, and status signalling means connected to said input/output interface logic, responsive to a predetermined state of another one of said control bits, and said second signalling means to inhibit operation of said interrupt requesting means, transfer status information to said central storage, and then render said device control block access means effective.
Claim 2
Dependent Claim
330 words
A data processing system comprising: central storage means for data, program instructions, including operate I/O instructions, and peripheral device control blocks comprised of a plurality of control fields, a peripheral device control unit including peripheral storage means for a peripheral device control block, input/output interface logic including a data bus, address bus, and control signal lines interconnecting said central storage and peripheral device control unit, a central processor connected to said central storage and said input/output interface logic, responsive to each said operate I/O instruction for initiating operation of said central storage and said interface logic for transferring to said peripheral device control unit a peripheral device control block, said peripheral device control block including in the control fields, a first field comprised of a plurality of control bits, a central storage data address field specifying a data field in central storage involved in the data transfer, a count field specifying the amount of data to be transferred, and a chained device control block address field specifying the central storage location of a succeeding device control block to be transferred after use of the current device control block; said peripheral device control unit including, device control block access means connected to said input/output interface logic, responsive to a predetermined state of one of said control bits and first signalling means indicating normal completion of use of the current device control block to access from said central storage the next succeeding device control block, interrupt requesting means connected to said input/output interface logic, responsive to a second signalling means indicating unusual completion of use of the current device control block to signal an interrupt request to said central processor, and status signalling means connected to said input/output interface logic, responsive to a predetermined state of another one of said control bits, and said second signalling means to inhibit operation of said interrupt requesting means, transfer status information to said central storage, and then render said device control block access means effective.
Claim 3
Dependent Claim
61 words
A data processing system in accordance with claim 1 wherein: said first signalling means is rendered effective when the device indicates end of transfer and the amount of data transferred equals said count field; and said second signalling means is rendered effective when the device indicates end of transfer and the amount of data transferred does not equal said count field.
Claim 4
Dependent Claim
30 words
A data processing system in accordance with claim 2 wherein: said status information includes the difference between the amount of data transferred and the amount specified by said count field.
Claim 5
Dependent Claim
59 words
A data processing system in accordance with claim 3 wherein: said peripheral device control block includes a further control field specifying a central storage address for residual status information, said residual status address and status information being transferred to said central storage for control thereof, over said data bus and said address bus, without intervention by said central processor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-10 | 1981-04-11 | 1981-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-10 | 1985-04-11 | 1985-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-10 | 1989-04-11 | 1989-10-11 | $7700.00 | Window Closed / Lapsed |