Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
64 words
In a digital communication system, an encoder comprising: means for encoding an information bit stream and producing a data bit stream, said data bit stream comprising a predetermined number of reference level bits, said data bit stream further comprising a predetermined number n of sync bits; said encoder further comprising concatenation means for replacing n of said reference level bits with said sync bits.
Claim 2
Dependent Claim
64 words
In a digital communication system, an encoder comprising: means for encoding an information bit stream and producing a data bit stream, said data bit stream comprising a predetermined number of reference level bits, said data bit stream further comprising a predetermined number n of sync bits; said encoder further comprising concatenation means for replacing n of said reference level bits with said sync bits.
Claim 3
Dependent Claim
45 words
The system of claim 1 further comprising a decoder for recovering said information bit stream from said data bit stream, said decoder comprising: means for recognizing a threshold number of said sync bits and, in response thereto, replacing said sync bits with reference level bits.
Claim 4
Dependent Claim
81 words
The system of claim 2 wherein the encoder further comprises means for convolutionally encoding said information bit stream with parity bits for correction of burst errors having a length as long as kB bits, kB of said parity bits occurring at the beginning of said data stream, jB bits occurring at the conclusion of said data stream; where k and j are predetermined integers, and wherein the concatenation means includes means for replacing said kB bits with said n sync bits.
Claim 5
Dependent Claim
116 words
The system of claim 3 wherein the encoder further comprises: an information bit register for storing a sequence of the information bits; a parity bit generator for modulo-2 adding predetermined pairs of the information bits stored in the information bit register, each modulo-2 addition comprising a parity bit; a parity bit register for storing a sequence of the parity bits; a sync bit memory for producing said n sync bits; means for transferring said n sync bits from said sync bit memory to said parity storage register responsive to a predetermined point in encoding said information bit stream; and switching means for sequentially outputting predetermined bits from said information bit register and said parity bit register.
Claim 6
Dependent Claim
111 words
The system of claim 4 wherein the decoder further comprises: a data stream register for storing a sequence of said data bit stream; a sync bit reference memory for producing said n sync bits; comparator means for monitoring said data stream register and comparing said stored data bit stream sequence with said sync bit reference memory, said comparator producing a control signal when a minimum number, q, of said data bits match said sync reference memory produced bits; first means responsive to said produced control signal for replacing said n sync bits with reference level bits; and second means responsive to said produced control signal for outputting said data stream register.
Claim 7
Dependent Claim
37 words
The system of claim 3 wherein said information bit stream is comprised of a series of messages, each message having a predetermined bit length, the encoder further comprising means for replacing said jB bits with sync bits.
Claim 8
Dependent Claim
29 words
The system of claim 1 wherein the encoding means comprises time diversity data transmission encoding means for repeating the information bits after said predetermined number of reference level bits.
Claim 9
Dependent Claim
172 words
In a digital communication system wherein an information bit stream is convolutionally encoded in a data bit stream, said encoding providing the capability of correcting for burst errors of as many as kB successive bits, where k is a predetermined integer, said burst error correction requiring that said data bit stream comprise kB reference level bits, said encoding also providing n synchronization bits, the communication system also having a decoder for processing the data bit stream and recovering the information bit stream, the decoder requiring recognition of at least a threshold number, q, of said synchronized bits and further requiring at least kB reference level bits for correction of a burst error having as many as kB successive error bits, the improvement comprising: said encoder further comprising means for replacing at least q of said kB reference level bits with at least q synchronization bits; and said decoder further comprising means for recognizing said at least q synchronization bits and, in response thereto, replace said q synchronization bits with reference level bits.
Claim 10
Dependent Claim
172 words
In a digital communication system wherein an information bit stream is convolutionally encoded in a data bit stream, said encoding providing the capability of correcting for burst errors of as many as kB successive bits, where k is a predetermined integer, said burst error correction requiring that said data bit stream comprise kB reference level bits, said encoding also providing n synchronization bits, the communication system also having a decoder for processing the data bit stream and recovering the information bit stream, the decoder requiring recognition of at least a threshold number, q, of said synchronized bits and further requiring at least kB reference level bits for correction of a burst error having as many as kB successive error bits, the improvement comprising: said encoder further comprising means for replacing at least q of said kB reference level bits with at least q synchronization bits; and said decoder further comprising means for recognizing said at least q synchronization bits and, in response thereto, replace said q synchronization bits with reference level bits.
Claim 11
Dependent Claim
121 words
The system of claim 8 wherein the encoder further comprises: an information bit register for storing a sequence of the information bits; a parity bit generator for modulo-2 adding predetermined pairs of the information bits stored in the information bit register, each modulo-2 addition comprising a parity bit; a parity bit register for storing a sequence of the parity bits; a sync bit memory for producing at least q sync bits; means for transferring said at least q sync bits from said sync bit memory to said parity storage register responsive to a predetermined point in the encoding of said information bit stream; and switching means for sequentially outputting predetermined bits in said information bit register and said parity bit register.
Claim 12
Dependent Claim
113 words
The system of claim 8 wherein the decoder further comprises: a data stream register for storing a sequence of said data bit stream; a sync bit reference memory for producing said n sync bits; comparator means for monitoring said data stream register and comparing said stored data bit stream sequence with said sync bit reference memory, said comparator producing a control signal when at least q of said data bits match with said synchronization reference memory produced bits; first means responsive to said produced control signal for replacing said at least q synchronization bits with reference level bits; and second means responsive to said produced control signal for outputting said data stream register.
Claim 13
Dependent Claim
19 words
The system of claim 8 wherein the encoding means replaces said kB reference level bits with n synchronization bits.
Claim 14
Dependent Claim
97 words
The system of claim 8 wherein said information bit stream is comprised of a series of messages, each message having a predetermined bit length, and wherein the burst error correction encoding further requires a number jB of reference level bits at the conclusion of each message, where j is a predetermined integer, the encoder further comprising means for replacing a predetermined number of said jB bits with sync bits; and the decoder further comprising means for recognizing a minimum number of said predetermined sync bits and, in response thereto, replacing said sync bits with reference level bits.