Simultaneous message framing and error detection

Claim 1

IN A DATA TRANSMISSION SYSTEM OF THE TYPE IN WHICH ERROR DETECTION IS ACCOMPLISHED BY AN ENCODER SHIFT REGISTER WHICH OPERATES UPON INCOMING DATA IN SUCH A WAY THAT AFTER ALL BITS OF A DATA POLYNOMIAL HAVE PASSED THROUGH THE ENCODER SHIFT REGISTER THE CONTENTS OF THE ENCODER REGISTER CONTAIN BITS CORRESPONDING TO THE REMAINDER OF THE DIVISION OF THE DATA POLYNOMIAL DIVIDED BY A CODING POLYNOMIAL, AND IN WHICH THE DATA POLYNOMIAL IS TRANSMITTED FOLLOWED BY THE REMAINDER BITS, THE DATA BITS PLUS REMAINDER BITS TOTALING N BITS, A DECORDER COMPRISING: MEANS FOR SEQUENTIALLY STORING N CONSECUTIVE BITS OF A SERIES OF RECEIVED DATA BITS; A LINEAR FEEDBACK SHFT REGISTER FOR REDUCING THE DATA POLYNOMIAL MODULO THE CODING POLYNOMIAL; MEANS RESPONSIVE TO SAID STORAGE MEANS FOR CONTINUOUSLY SUBTRACTING, MODULO THE CODING POLYNOMIAL, FROM THE CONTENTS OF SAID SHIFT REGISTER THE VALUE OF A DATA BIT WHICH APPEARED AT THE INPUT TO SAID LINEAR FEEDBACK SHIFT REGISTER N BITS PREVIOUSLY STORED IN SAID STORAGE MEANS; AND MEANS FOR CONTINUOUSLY COMPARING THE CONTENTS OF SAID LINEAR FEEDBACK SHIFT REGISTER WITH A TEST PATTERN AND FOR GENERATING AN OUTPUT SIGNAL WHEN THE CONTENTS OF THE LINEAR FEEDBACK SHIFT REGISTER ARE EQUAL TO THE TEST PATTERN.