Oversized data detection hardware for data processors which store data at variable length destinations

Claim 2

In a data processing system for storing variable length operands in variable length destinations, wherein the destination length may be less than the length of the operand to be stored, the combination comprising: circuitry for providing an indication of the destination length; circuitry responsive to the operand to be stored for providing status signals for different parts of the operand field; and circuitry responsive to the destination length indication and to the status signals for generating a size exception indication when the part of the operand field located outside of the destination length contains significant data.

Claim 3

In a data processing system having an arithmetic unit for performing arithmetic operations on variable length operands and sending the results to variable length destinations, wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the destination length; circuitry coupled to the arithmetic unit for providing status signals for different parts of the arithmetic unit output field; and circuitry responsive to the destination length indication and to the status signals for generating a size exception indication when the part of the operand field located outside of the destination length contains significant data.

Claim 4

In a data processing system having an arithmetic unit for performing arithmetic operations on variable length operands and sending the results to variable length destinations, wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the destination length; circuitry coupled to the arithmetic unit for providing status signals for different parts of the arithmetic unit output field; and circuitry responsive to the destination length indication and to the status signals for generating a size exception indication when the part of the operand field located outside of the destination length contains significant data.

Claim 5

In a data processing system having an arithmetic unit and responsive to data processing instructions for performing arithmetic operations on variable length operands and sending the results to variable length destinations, wherein the operand and destination lengths are specified in the instruction and wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the destination length specified in the instruction; circuitry coupled to the arithmetic unit for providing status signals for different parts of the arithmetic unit output field; and circuitry responsive to the destination length indication and to the status signals for generating a size exception indication when the part of the arithmetic unit output field located outside of the destination length contains significant data.

Claim 6

In a data processing system having an arithmetic unit and responsive to data processing instructions for performing arithmetic operations on variable length operands and sending the results to variable length destinations, wherein the operand and destination lengths are specified in the instruction and wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the destination length specified in the instruction; circuitry coupled to the arithmetic unit for providing status signals for different parts of the arithmetic unit output field; and circuitry responsive to the destination length indication and to the status signals for generating a size exception indication when the part of the arithmetic unit output field located outside of the destination length contains significant data.

Claim 7

The combination of claim 3 wherein the size exception generating circuitry is operative to generate the size exception indication during the same machine control cycle during which the arithmetic unit performs the arithmetic operation which gives rise to the size exception.

Claim 8

In a data processing system having a multibyte parallel arithmetic unit and responsive to data processing instructions for performing arithmetic operations on variable length operands and sending the results to variable length destinations, wherein the operand and destination lengths in byte units are specified in the instruction and wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the byte unit destination length specified in the instruction; circuitry coupled to the arithmetic unit for providing status signals for the different bytes of the arithmetic unit output field; and circuitry responsive to the destination length indication and to the status signals for generating a size exception indication when the part of the arithmetic unit output field located outside of the destination length contains significant data.

Claim 9

In a data processing system having a multibyte parallel arithmetic unit and responsive to data processing instructions for performing arithmetic operations on variable length operands and sending the results to variable length destinations, wherein the operand and destination lengths in byte units are specified in the instruction and wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the byte unit destination length specified in the instruction; circuitry coupled to the arithmetic unit for providing status signals for the different bytes of the arithmetic unit output field; and circuitry responsive to the destination length indication and to the status signals for generating a size exception indication when the part of the arithmetic unit output field located outside of the destination length contains significant data.

Claim 10

The combination of claim 5 wherein the size exception generating circuitry is operative to generate the size exception indication during the same machine control cycle during which the arithmetic unit performs the arithmetic operation which gives rise to the size exception.

Claim 11

In a data processing system having a multibyte parallel arithmetic unit and responsive to data processing instructions for performing arithmetic operations on variable length operands and sending the results to variable length destinations, wherein the operand and destination lengths in byte units are specified in the instruction and wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the byte unit destination length specified in the instruction; status signal generating circuitry coupled to the arithmetic unit for producing status signals for the different bytes of the arithmetic unit output field; selector circuitry responsive to the destination length indication for selecting the status signals for that part of the arithmetic unit output field which is located outside of the destination length; and circuitry responsive to the selected status signals for generating a size exception indication when such selected status signals indicate the presence of significant data.

Claim 12

In a data processing system having a multibyte parallel arithmetic unit and responsive to data processing instructions for performing arithmetic operations on variable length operands and sending the results to variable length destinations, wherein the operand and destination lengths in byte units are specified in the instruction and wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the byte unit destination length specified in the instruction; status signal generating circuitry coupled to the arithmetic unit for producing status signals for the different bytes of the arithmetic unit output field; selector circuitry responsive to the destination length indication for selecting the status signals for that part of the arithmetic unit output field which is located outside of the destination length; and circuitry responsive to the selected status signals for generating a size exception indication when such selected status signals indicate the presence of significant data.

Claim 13

In a data processing system having a multibyte parallel arithmetic unit and responsive to data processing instructions for performing arithmetic operations on variable length binary coded decimal operands in either zoned or packed format and sending the results to variable length destinations, wherein the operand and destination lengths in byte units are specified in the instruction and wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the byte unit destination length specified in the instruction; circuitry coupled to the arithmetic unit for producing a status signal for each 4-bit portion of the arithmetic unit output field for indicating whether or not all the bits in such four-bit portion are zeros and including circuitry responsive to a zoned decimal control signal for forcing the status signals for the four-bit zone field portions to give an all zero indication when the arithmetic unit is processing zoned decimal operands; and circuitry responsive to the destination length indication and to the status signals for generating a size exception indication when any of the status signals for the part of the arithmetic unit output field located outside of the destination length indicates the presence of a non-zero bit.

Claim 14

In a data processing system having a multibyte parallel arithmetic unit and responsive to data processing instructions for performing arithmetic operations on variable length binary coded decimal operands in either zoned or packed format and sending the results to variable length destinations, wherein the operand and destination lengths in byte units are specified in the instruction and wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the byte unit destination length specified in the instruction; circuitry coupled to the arithmetic unit for producing a status signal for each 4-bit portion of the arithmetic unit output field for indicating whether or not all the bits in such four-bit portion are zeros and including circuitry responsive to a zoned decimal control signal for forcing the status signals for the four-bit zone field portions to give an all zero indication when the arithmetic unit is processing zoned decimal operands; and circuitry responsive to the destination length indication and to the status signals for generating a size exception indication when any of the status signals for the part of the arithmetic unit output field located outside of the destination length indicates the presence of a non-zero bit.

Claim 15

In a data processing system having a parallel arithmetic unit and responsive to data processing instructions for performing arithmetic operations on variable length signed binary operands and sending the results to variable length destinations, wherein the operand and destination lengths are specified in the instruction and wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the destination length specified in the instruction; binary sign bit circuitry coupled to the output of the arithmetic unit and responsive to the destination length indication for selecting the sign bit location in the arithmetic unit output field and producing a polarity indication indicating whether the destination data has a positive or a negative sign; and size exception circuitry coupled to the output of the arithmetic unit and responsive to the polarity indication and the destination length indication for generating a size exception indication if the polarity indication is positive and the bits of the arithmetic unit output field located outside of the destination length are not all zeros or if the polarity indication is negative and the non-destination bits are not all ones.

Claim 16

In a data processing system having a parallel arithmetic unit and responsive to data processing instructions for performing arithmetic operations on variable length signed binary operands and sending the results to variable length destinations, wherein the operand and destination lengths are specified in the instruction and wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the destination length specified in the instruction; binary sign bit circuitry coupled to the output of the arithmetic unit and responsive to the destination length indication for selecting the sign bit location in the arithmetic unit output field and producing a polarity indication indicating whether the destination data has a positive or a negative sign; and size exception circuitry coupled to the output of the arithmetic unit and responsive to the polarity indication and the destination length indication for generating a size exception indication if the polarity indication is positive and the bits of the arithmetic unit output field located outside of the destination length are not all zeros or if the polarity indication is negative and the non-destination bits are not all ones.

Claim 17

In a data processing system having a multibyte parallel arithmetic unit and responsive to data processing instructions for performing arithmetic operations on variable length signed binary operands and sending the results to variable length destinations, wherein the operand and destination lengths in byte units are specified in the instruction and wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the byte unit destination length specified in the instruction; status signal generating circuitry coupled to the arithmetic unit for producing first and second status signals for each byte of the arithmetic unit output field, the first status signal being a zero indicating status signal for indicating whether or not all the bits in the byte are zeros and the second status signal being a one indicating status signal for indicating whether or not all the bits in the byte are ones; binary sign bit circuitry coupled to the output of the arithmetic unit and responsive to the destination length indication for selecting the sign bit location in the arithmetic unit output field and producing a polarity indication indicating whether the destination data has a positive or a negative sign; and size exception circuitry responsive to the zero and one indicating status signals, the polarity indication and the destination length indication for generating a size exception indication if the polarity indication is positive and the bits of the arithmetic unit output field located outside of the destination length are not all zeros or if the polarity indication is negative and the non-destination bits are not all ones.

Claim 18

In a data processing system having a multibyte parallel arithmetic unit and responsive to data processing instructions for performing arithmetic operations on variable length signed binary operands and sending the results to variable length destinations, wherein the operand and destination lengths in byte units are specified in the instruction and wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the byte unit destination length specified in the instruction; status signal generating circuitry coupled to the arithmetic unit for producing first and second status signals for each byte of the arithmetic unit output field, the first status signal being a zero indicating status signal for indicating whether or not all the bits in the byte are zeros and the second status signal being a one indicating status signal for indicating whether or not all the bits in the byte are ones; binary sign bit circuitry coupled to the output of the arithmetic unit and responsive to the destination length indication for selecting the sign bit location in the arithmetic unit output field and producing a polarity indication indicating whether the destination data has a positive or a negative sign; and size exception circuitry responsive to the zero and one indicating status signals, the polarity indication and the destination length indication for generating a size exception indication if the polarity indication is positive and the bits of the arithmetic unit output field located outside of the destination length are not all zeros or if the polarity indication is negative and the non-destination bits are not all ones.

Claim 19

In a data processing system having a multibyte parallel arithmetic unit and responsive to data processing instructions for performing arithmetic operations on variable length operands in either decimal or binary format and sending the results to variable length destinations, wherein the operand and destination lengths in byte units are specified in the instruction and wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the byte unit destination length specified in the instruction; status signal generating circuitry coupled to the arithmetic unit for producing first and second status signals for each byte of the arithmetic unit output field; decimal format size exception circuitry responsive to the destination length indication, the first status signals and a decimal format control signal for generating a size exception indication when the arithmetic unit is processing decimal operands and the part of the arithmetic unit output field located outside of the destination length contains significant data; and binary format size exception circuitry responsive to the destination length indication, the first and second status signals and a binary format control signal for generating a size exception indication when the arithmetic unit is processing binary operands and the part of the arithmetic unit output field located outside of the destination length contains significant data.

Claim 20

In a data processing system having a multibyte parallel arithmetic unit and responsive to data processing instructions for performing arithmetic operations on variable length operands in either decimal or binary format and sending the results to variable length destinations, wherein the operand and destination lengths in byte units are specified in the instruction and wherein the destination length may be less than the length of at least one of the operands, the combination comprising: circuitry for providing an indication of the byte unit destination length specified in the instruction; status signal generating circuitry coupled to the arithmetic unit for producing first and second status signals for each byte of the arithmetic unit output field; decimal format size exception circuitry responsive to the destination length indication, the first status signals and a decimal format control signal for generating a size exception indication when the arithmetic unit is processing decimal operands and the part of the arithmetic unit output field located outside of the destination length contains significant data; and binary format size exception circuitry responsive to the destination length indication, the first and second status signals and a binary format control signal for generating a size exception indication when the arithmetic unit is processing binary operands and the part of the arithmetic unit output field located outside of the destination length contains significant data.

Claim 21

In a data processing system having a parallel arithmetic unit of fixed width and responsive to data processing instructions for performing arithmetic operations on variable length operands and sending the results to variable length destinations, wherein the operand and destination lengths are specified by plural-bit length fields in the instruction, the destination length may be less than the length of at least one of the operands and, for those cases where the operand length is greater than the arithmetic unit width, the lower order parts of the operands are processed during a first pass through the arithmetic unit and the higher order parts of the operands are processed during a second pass through the arithmetic unit, the combination comprising: circuitry for providing indications of the destination length bits in the instruction; circuitry coupled to the arithmetic unit for providing status signals for different parts of the arithmetic unit output field; size exception circuitry responsive to the lower order destination length bits and to the status signals for generating a size exception indication when the part of the arithmetic unit output field located outside of the destination length specified by these lower order bits contains significant data; output circuitry for making the size exception indication available to a control section of the data process system; and first pass-second pass circuitry located intermediate the size exception circuitry and the output circuitry and responsive to a higher order destination length bit and to a first pass control signal from the control section for inhibiting transfer of the size exception indication to the output circuitry for the case of a first pass with operands of length greater than the arithmetic unit width.

Claim 22

In a data processing system having a parallel arithmetic unit of fixed width and responsive to data processing instructions for performing arithmetic operations on variable length operands and sending the results to variable length destinations, wherein the operand and destination lengths are specified by plural-bit length fields in the instruction, the destination length may be less than the length of at least one of the operands and, for those cases where the operand length is greater than the arithmetic unit width, the lower order parts of the operands are processed during a first pass through the arithmetic unit and the higher order parts of the operands are processed during a second pass through the arithmetic unit, the combination comprising: circuitry for providing indications of the destination length bits in the instruction; circuitry coupled to the arithmetic unit for providing status signals for different parts of the arithmetic unit output field; size exception circuitry responsive to the lower order destination length bits and to the status signals for generating a size exception indication when the part of the arithmetic unit output field located outside of the destination length specified by these lower order bits contains significant data; output circuitry for making the size exception indication available to a control section of the data process system; and first pass-second pass circuitry located intermediate the size exception circuitry and the output circuitry and responsive to a higher order destination length bit and to a first pass control signal from the control section for inhibiting transfer of the size exception indication to the output circuitry for the case of a first pass with operands of length greater than the arithmetic unit width.