Interrupt circuitry for microprocessor chip

Claim 1

In a microprocessor, circuitry for effecting execution of an interrupt operation of said microprocessor in response to an interrupt request signal, comprising: data bus means for transferring digital information, said data bus means being coupled to a memory means having an interrupt routine program stored therein; register storage means coupled to said data bus means for temporarily storing digital information in accordance with execution of various instructions by said microprocessor, including an instruction for setting an interrupt mask bit; an interrupt request conductor for conducting said interrupt request signal; instruction register means coupled to said data bus means for temporarily storing each instruction as it is received from said data bus means; instruction decode means coupled to said instruction register means for controlling said register storage means and said data bus means to effect execution of the instruction stored in said instruction register means; storage means coupled to said interrupt request conductor and said data bus means for storing said interrupt mask bit received from said data bus means in accordance with execution of said instruction for setting said interrupt mask bit; gating means, coupled to said storage means and to said interrupt request conductor, for generating an interrupt enable signal responsive to said interrupt mask bit; interrupt means, coupled to said gating means and to said data bus means, for inhibiting said temporary storing of the next instruction to be executed; means responsive to said interrupt enable signal for internally generating a fixed code instruction within said instruction register means; and circuit means in said instruction decode means for effecting transferring digital information in said register storage means to said memory means and causing said microprocessor to branch to said interrupt routine program.