Patent US1717171A successfully refreshed from Google Patents.
US4003024A
Expired / Lapsed
US
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Two-dimensional binary data enhancement system
Assignee: Printrak International Inc
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Filing: 1975-10-14
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Granted: 1977-01-11
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Expires: 1995-10-14
Abstract
Abstract A system for enhancing a binary data bit stream derived from a two-dimensional pattern image wherein, in a preferred embodiment, each data bit in the bit stream and a preselected group of bits associated therewith are sequentially stored in a first location and in associated preselected locations, respectively, of a storage circuit of a first enhancement stage. The bits associated with each data bit are utilized as an address to cause a read only memory to develop a decision bit as a function of the address. A gating circuit develops an output bit in response to each data bit and its associated decision bit. The sequence of output bits forms an enhanced data bit stream which appears at the output of the first enhancement stage for further application to one or more additional cascaded enhancement stages.
Inventors
- 👤 John P. Riganati
- 👤 Visvaldis A. Vitols
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:28
CPC Classifications
G; G06; G06V; G06V40/00; G06V40/10; G06V40/12; G06V40/1347; G06V10/00; G06V10/20; G06V10/34
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
188 words
A system for enhancing the bits in two-dimensional binary data, said system comprising: means for sequentially storing a data bit and bits associated therewith in preselected storage locations; and means for sequentially developing an output bit for each data bit, the state of the output bit being a function of the pattern of the bits stored in the preselected storage locations, said developing means comprising memory means for developing first and second decision bits as a function of the states of the bits associated with the data bit and gating means for selecting one of the first and second decision bits for the output bit as a function of the binary state of the data bit, said gating means comprising: a first gate circuit for developing the output bit; a second gate circuit for passing the first decision bit through said first gate circuit as the output bit when the data bit is in a first binary state; and a third gate circuit for passing the second decision bit through the first gate circuit as the output bit when the data bit is in a second binary state.
Claim 2
Independent Claim
188 words
A system for enhancing the bits in two-dimensional binary data, said system comprising: means for sequentially storing a data bit and bits associated therewith in preselected storage locations; and means for sequentially developing an output bit for each data bit, the state of the output bit being a function of the pattern of the bits stored in the preselected storage locations, said developing means comprising memory means for developing first and second decision bits as a function of the states of the bits associated with the data bit and gating means for selecting one of the first and second decision bits for the output bit as a function of the binary state of the data bit, said gating means comprising: a first gate circuit for developing the output bit; a second gate circuit for passing the first decision bit through said first gate circuit as the output bit when the data bit is in a first binary state; and a third gate circuit for passing the second decision bit through the first gate circuit as the output bit when the data bit is in a second binary state.
Claim 3
Dependent Claim
24 words
The system of claim 1 wherein: said first gate circuit is an OR gate; and said second and third gate circuits are AND gates.
Claim 4
Independent Claim
164 words
A system for enhancing the bits in two-dimensional binary data, said system comprising: means for sequentially storing a data bit and bits associated therewith in preselected storage locations; and means for sequentially developing an output bit for each data bit, the state of the output bit being a function of the pattern of the bits stored in the preselected storage locations, said developing means comprising memory means for developing first and second decision bits as a function of the states of the bits associated with the data bit and gating means for selecting one of the first and second decision bits for the output as a function of the binary state of the data bit, said memory means comprising: a first memory circuit responsive to the states of the bits associated with the data bit for developing the first decision bit; and a second memory circuit responsive to the states of the bits associated with the data bit for developing the second decision bit.
Claim 5
Independent Claim
164 words
A system for enhancing the bits in two-dimensional binary data, said system comprising: means for sequentially storing a data bit and bits associated therewith in preselected storage locations; and means for sequentially developing an output bit for each data bit, the state of the output bit being a function of the pattern of the bits stored in the preselected storage locations, said developing means comprising memory means for developing first and second decision bits as a function of the states of the bits associated with the data bit and gating means for selecting one of the first and second decision bits for the output as a function of the binary state of the data bit, said memory means comprising: a first memory circuit responsive to the states of the bits associated with the data bit for developing the first decision bit; and a second memory circuit responsive to the states of the bits associated with the data bit for developing the second decision bit.
Claim 6
Dependent Claim
17 words
The system of claim 3 wherein said first and second memory circuits are read only memory circuits.
Claim 7
Dependent Claim
78 words
The system of claim 3 wherein said gating means comprises: a first gate circuit for developing the output bit; a second gate circuit for passing the first decision bit through said first gate circuit as the output bit when the data bit is in a first binary state; and a third gate circuit for passing the second decision bit through the first gate circuit as the output bit when the data bit is in a second binary state.
Claim 8
Dependent Claim
24 words
The system of claim 5 wherein: said first gate circuit is an OR gate; and said second and third gate circuits are AND gates.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-01-11 | 1980-07-12 | 1981-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-01-11 | 1984-07-12 | 1985-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-01-11 | 1988-07-12 | 1989-01-11 | $7700.00 | Window Closed / Lapsed |